公开(公告)号：US20240161860A1

公开(公告)日：2024-05-16

申请号：US18113165

申请日：2023-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MYEONGJIN OH ,  KYUNGJIN PARK ,  YONGSUK CHOI

IPC: G11C29/54 ,  G11C29/50

CPC classification number: G11C29/54 ,  G11C29/50004

Abstract: A semiconductor device includes: a memory test circuit that outputs a fourth signal based on a logic level of a second signal corresponding to a first signal output by a host and a logic level of a third signal; a memory device that becomes active or inactive based on a logic level of the fourth signal; and a test logic that outputs the third signal and performs a retention test on the memory device based on the logic level of the second signal.

公开(公告)号：US20240379386A1

公开(公告)日：2024-11-14

申请号：US18402844

申请日：2024-01-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YONGSUK CHOI ,  Ilkyu Jeong ,  Hyunwoong Hwang ,  Kyung-Won Kang ,  Dong-Wook Kim ,  Seok Heo

IPC: H01L21/67 ,  H01L21/677

Abstract: A substrate processing system includes a cluster module having substrate processing devices, a load port through which a substrate is loaded, and a substrate cleaning device between the cluster module and the load port, the substrate cleaning device being configured to clean the substrate processed in the substrate processing devices, and the substrate cleaning device including a substrate cleaner having a cleaning chuck to support the substrate, and a cleaning nozzle configured to spray a fluid toward the cleaning chuck.

公开(公告)号：US20220293649A1

公开(公告)日：2022-09-15

申请号：US17455246

申请日：2021-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAKYU CHOI ,  YONGSUK CHOI ,  KEO-SUNG PARK ,  DONGWOOK WON

IPC: H01L27/146

Abstract: A method of manufacturing an image sensor includes forming a first dopant region having a second conductivity type in a semiconductor substrate including first and second surfaces. The semiconductor substrate has a first conductivity type different from the second conductivity type. The method further includes forming a pixel isolation structure defining pixel regions in the semiconductor substrate, forming a vertical trench by patterning the first surface in each of the pixel regions, forming a mask pattern exposing each of the pixel regions on the first surface, in which the mask pattern includes a residual mask pattern filling at least a portion of the vertical trench, forming a second dopant region having the second conductivity type in the semiconductor substrate by using the mask pattern as an ion-implantation mask, in which the second dopant region is adjacent to the vertical trench, and forming a transfer gate electrode in the vertical trench.