公开(公告)号：US20240079328A1

公开(公告)日：2024-03-07

申请号：US18133198

申请日：2023-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejun YOO ,  Changbeom KIM ,  Taejung SEOL

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L23/5286 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: A semiconductor device includes a logic cell region on a substrate, an interconnection layer on the logic cell region, the interconnection layer including a plurality of metal layers on the logic cell region, and a first vertical structure in the interconnection layer, where the first vertical structure vertically connects the logic cell region to an uppermost metal layer of the plurality of metal layers, each of the plurality of unit structures includes a lower via, a lower interconnection line, an upper via, and an upper interconnection line, the lower interconnection line and the upper interconnection line of each respective unit structure of the plurality of unit structures cross each other, and the upper interconnection line of each of the plurality of unit structures includes a first upper interconnection line.