公开(公告)号：US20220278011A1

公开(公告)日：2022-09-01

申请号：US17749825

申请日：2022-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghawn BAE ,  Doohwan LEE ,  Jooyoung CHOI

IPC: H01L23/31 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/373 ,  H01L23/367

Abstract: Provided is method of manufacturing a semiconductor device. The method includes: forming a metal layer on a carrier; forming a conductor pattern layer on the metal layer; mounting a semiconductor chip on a tape; forming an encapsulant covering the semiconductor chip; attaching the conductor pattern layer to the encapsulant; removing the tape; and forming a connection structure electrically connected to the semiconductor chip in an area from which the tape is removed.

公开(公告)号：US20210257337A1

公开(公告)日：2021-08-19

申请号：US17019616

申请日：2020-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongjin PARK ,  Sunghawn BAE ,  Won CHOI

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L25/10

Abstract: A semiconductor package includes: a redistribution substrate; a frame including first and second vertical connection conductors, and having a through-hole; first and second semiconductor chips; an encapsulant; a second redistribution structure disposed on the encapsulant, a conductive wire electrically connecting the second semiconductor chip and the second vertical connection conductor; and a vertical connection via penetrating a portion of the encapsulant, and electrically connecting the second redistribution structure and the first vertical connection conductor. The first semiconductor chip is connected to the second vertical connection conductor by the first redistribution structure.

公开(公告)号：US20200152535A1

公开(公告)日：2020-05-14

申请号：US16672652

申请日：2019-11-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghawn BAE ,  Doohwan LEE ,  Jooyoung CHOI

IPC: H01L23/31 ,  H01L21/48 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00

Abstract: The invention provides a semiconductor package, which may include a connection structure including one or more redistribution layers. A semiconductor chip is disposed on the connection structure and has an active surface on which a connection pad electrically connected to the redistribution layer is disposed and an inactive surface opposite to the active surface. An encapsulant is disposed on the connection structure and covers at least a portion of the inactive surface of the semiconductor chip. A conductor pattern layer is embedded in the encapsulant such that one exposed surface of the conductor pattern layer is exposed from the encapsulant. A metal layer is disposed on the encapsulant and covers the one exposed surface of the conductor pattern layer.

公开(公告)号：US20220367417A1

公开(公告)日：2022-11-17

申请号：US17863695

申请日：2022-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongjin PARK ,  Sunghawn BAE ,  Won CHOI

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/10 ,  H01L25/18

Abstract: A semiconductor package includes: a redistribution substrate; a frame including first and second vertical connection conductors, and having a through-hole; first and second semiconductor chips; an encapsulant; a second redistribution structure disposed on the encapsulant, a conductive wire electrically connecting the second semiconductor chip and the second vertical connection conductor; and a vertical connection via penetrating a portion of the encapsulant, and electrically connecting the second redistribution structure and the first vertical connection conductor. The first semiconductor chip is connected to the second vertical connection conductor by the first redistribution structure.

公开(公告)号：US20200168537A1

公开(公告)日：2020-05-28

申请号：US16684936

申请日：2019-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghawn BAE

IPC: H01L23/498 ,  H01L23/13 ,  H01L23/31

Abstract: The present invention provides a fan-out semiconductor package, and the fan-out semiconductor package includes a semiconductor chip, an encapsulant covering the semiconductor chip, a connection structure disposed below the semiconductor chip and including a redistribution layer, and first and second metal pattern layers disposed on different levels on the semiconductor chip. The first metal pattern layer is to electrically connect to an electrical connection member such as a frame, provided for electrical connection of the fan-out semiconductor package in a vertical direction through a path via the second metal pattern layer.