公开(公告)号：US20240292594A1

公开(公告)日：2024-08-29

申请号：US18384407

申请日：2023-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SangHyun LEE ,  Kiseok LEE ,  Seokhan PARK ,  Sung-Min PARK ,  Iljae SHIN ,  Dongjun LEE ,  Jinwoo HAN

IPC: H10B12/00

CPC classification number: H10B12/30 ,  H10B12/05 ,  H10B12/50

Abstract: A semiconductor memory device includes a semiconductor substrate; a stack structure that includes word lines and interlayer dielectric patterns that are alternately stacked on the semiconductor substrate; an etch stop layer on the stack structure; semiconductor patterns that penetrate the word lines; a bit line in contact with the semiconductor patterns; capping dielectric patterns between the bit line and the word lines, the capping dielectric patterns covering sidewalls of the word lines; and a data storage element on the semiconductor substrate, wherein a level of a bottom surface of the etch stop layer is the same as a level of a top surface of the data storage element.