公开(公告)号：US20210313272A1

公开(公告)日：2021-10-07

申请号：US17350878

申请日：2021-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： EUIYEOL KIM ,  SUN-HYUN KIM ,  HEEWOO PARK

IPC: H01L23/538 ,  H01L23/522 ,  H01L21/768 ,  H01L25/065 ,  H01L23/528

Abstract: A semiconductor device may include first and second sub chips stacked sequentially and a through contact electrically connecting the first and second sub chips to each other. Each of the first and second sub chips may include a substrate and a plurality of interconnection lines, which are interposed between the substrates. The interconnection lines of the second sub chip may include first and second interconnection lines having first and second openings, respectively, which are horizontally offset from each other. The through contact may be extended from the substrate of the second sub chip toward the first sub chip and may include an auxiliary contact, which is extended toward the first sub chip through the first and second openings and has a bottom surface higher than a top surface of the uppermost one of the interconnection lines of the first sub chip.

公开(公告)号：US20200266150A1

公开(公告)日：2020-08-20

申请号：US16553018

申请日：2019-08-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： EUIYEOL KIM ,  SUN-HYUN KIM ,  HEEWOO PARK

IPC: H01L23/538 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H01L21/768

Abstract: A semiconductor device may include first and second sub chips stacked sequentially and a through contact electrically connecting the first and second sub chips to each other. Each of the first and second sub chips may include a substrate and a plurality of interconnection lines, which are interposed between the substrates. The interconnection lines of the second sub chip may include first and second interconnection lines having first and second openings, respectively, which are horizontally offset from each other. The through contact may be extended from the substrate of the second sub chip toward the first sub chip and may include an auxiliary contact, which is extended toward the first sub chip through the first and second openings and has a bottom surface higher than a top surface of the uppermost one of the interconnection lines of the first sub chip.