公开(公告)号：US20230058920A1

公开(公告)日：2023-02-23

申请号：US17876144

申请日：2022-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mallikarjun Shivappa BIDARI ,  Divakar KULKARNI ,  Raju Siddappa UDAVA ,  Shashank VIMAL ,  Tushar VRIND ,  Venkata Raju INDUKURI ,  Harish Kumar Veerappanchatram SUNDARAMURTHY ,  Rajiv HASIJA

IPC: G06F9/52 ,  G06F9/38 ,  G06F9/48

Abstract: A multicore computing device includes a memory and a processor coupled to the memory. The processor includes plural cores and a multiple input multiple output (MIMO) block coupled to the cores. The MIMO block receives a halt request from a first core of the cores, transmits a core-halt request to one or more other cores other than the first core, to halt execution of the one or more other cores, and permits the first core to lock with a shared resource.