公开(公告)号：US20230113615A1

公开(公告)日：2023-04-13

申请号：US17895227

申请日：2022-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WONJAE SHIN ,  SUNG-JOON KIM ,  HEEDONG KIM ,  MINSU BAE ,  ILWOONG SEO ,  MIJIN LEE ,  SEUNG JU LEE ,  HYAN SUK LEE ,  INSU CHOI ,  KIDEOK HAN

IPC: H03M13/19 ,  G11C11/408 ,  G11C11/4096 ,  H03M13/00

Abstract: A memory system includes a memory module that includes a first memory device through a fourth memory device and a first error correction code (ECC) device, and a memory controller that exchanges first user data with each of the first memory device through the fourth memory device through 8 data lines and exchanges first ECC data with the first ECC device through 4 data lines. The memory controller includes an ECC engine that corrects a 32-random bit error of the first user data, based on the first ECC data.