公开(公告)号：US09191599B2

公开(公告)日：2015-11-17

申请号：US13778591

申请日：2013-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yu-Jin Park ,  Kyo-Jin Choo ,  Ji-Hun Shin ,  Ji-Min Cheon ,  Jin-Ho Seo ,  Seog-Heon Ham

IPC: H04N5/335 ,  H04N5/00 ,  H04N5/378 ,  H04N5/357

CPC classification number: H04N5/378 ,  H04N5/3575

Abstract: A correlated double sampling (CDS) circuit included in an image sensor includes a sampling unit and a timing controlled band-limitation (TCBL) unit. The sampling unit is configured to generate an output signal by performing a CDS operation with respect to a reset component of an input signal and an image component of the input signal based on a ramp signal, the input signal being provided from a pixel array included in the image sensor. The TCBL unit is connected to the sampling unit, and is configured to remove noise from the output signal based on a timing control signal. The timing control signal is activated during a first comparison duration, in which a first comparison operation is performed with respect to the ramp signal and the reset component of the input signal, and during a second comparison duration, in which a second comparison operation is performed with respect to the ramp signal and the image component of the input signal.

Abstract translation: 包括在图像传感器中的相关双采样（CDS）电路包括采样单元和定时控制带限（TCBL）单元。 采样单元被配置为通过基于斜坡信号对输入信号的复位分量和输入信号的图像分量执行CDS操作来产生输出信号，该输入信号从包括在 图像传感器。 TCBL单元连接到采样单元，并且被配置为基于定时控制信号从输出信号中去除噪声。 定时控制信号在第一比较持续时间期间被激活，其中相对于斜坡信号和输入信号的复位分量执行第一比较操作，并且在执行第二比较操作的第二比较持续时间期间 相对于斜坡信号和输入信号的图像分量。

公开(公告)号：US09554073B2

公开(公告)日：2017-01-24

申请号：US14488637

申请日：2014-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun-Young Jin ,  Kyo-Jin Choo ,  Yu-Jin Park ,  Han-Kook Cho

IPC: H04N5/335 ,  H04N5/378

CPC classification number: H04N5/378 ,  H04N5/3355

Abstract: An integrated circuit comprises a first signal transfer block comprising first through (M)-th aligning blocks that are cascade-coupled to produce first aligned control signals through (M)-th aligned control signals, respectively, by aligning first control signals with a clock signal, wherein M is an integer greater than one, and a functional block divided into first through (M)-th sub-functional blocks configured to perform a same function in parallel, each of the first through (M)-th sub-functional blocks operating according to corresponding ones of the first aligned control signals through (M)-th aligned control signals generated by the first through (M)-th aligning blocks.

Abstract translation: 集成电路包括第一信号传输块，其包括通过（M）第一对准块级联耦合以分别通过（M）对准的控制信号产生第一对准的控制信号，通过将第一控制信号与时钟 信号，其中M是大于1的整数，以及分配成并行执行相同功能的第一至第（M）个子功能块的功能块，第一至第（M）个子功能 根据由第一到第（M）个对准块产生的（M）对准的控制信号，根据第一对准的控制信号中的相应的一个控制信号进行操作。