公开(公告)号：US20230139574A1

公开(公告)日：2023-05-04

申请号：US17851289

申请日：2022-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNGGUN YOU ,  Beomjin Park ,  Sughyun Sung ,  Hojin Lee ,  Dongwon Kim ,  Donggyu Lee ,  Myoung-Sun Lee ,  Keun Hwi Cho ,  Hanbyul Choi ,  Jiyong Ha

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: A semiconductor device includes: an active pattern on a substrate, wherein the active pattern includes a plurality of channel layers stacked on one another; a plurality of source/drain patterns spaced apart from each other in a first direction and disposed on the active pattern, wherein the plurality of source/drain patterns are connected to each other through the plurality of channel layers; and first and second gate electrodes at least partially surrounding the channel layers and extending in a second direction, wherein the second direction intersects the first direction, wherein the active pattern has a first sidewall and a second sidewall that faces the first sidewall, and wherein a first distance between the first sidewall of the active pattern and an outer sidewall of the first gate electrode is different from a second distance between the second sidewall of the active pattern and an outer sidewall of the second gate electrode.

公开(公告)号：US12237391B2

公开(公告)日：2025-02-25

申请号：US17851289

申请日：2022-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggun You ,  Beomjin Park ,  Sughyun Sung ,  Hojin Lee ,  Dongwon Kim ,  Donggyu Lee ,  Myoung-Sun Lee ,  Keun Hwi Cho ,  Hanbyul Choi ,  Jiyong Ha

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes: an active pattern on a substrate, wherein the active pattern includes a plurality of channel layers stacked on one another; a plurality of source/drain patterns spaced apart from each other in a first direction and disposed on the active pattern, wherein the plurality of source/drain patterns are connected to each other through the plurality of channel layers; and first and second gate electrodes at least partially surrounding the channel layers and extending in a second direction, wherein the second direction intersects the first direction, wherein the active pattern has a first sidewall and a second sidewall that faces the first sidewall, and wherein a first distance between the first sidewall of the active pattern and an outer sidewall of the first gate electrode is different from a second distance between the second sidewall of the active pattern and an outer sidewall of the second gate electrode.