公开(公告)号：US20240085469A1

公开(公告)日：2024-03-14

申请号：US18244559

申请日：2023-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seong Kwan LEE ,  Min Ho KANG ,  Hyung-Sun RYU ,  Cheol Min PARK ,  Jun Yeon WON ,  Jae Moo CHOI

IPC: G01R31/26

CPC classification number: G01R31/2607

Abstract: A transmitting and receiving circuit may include a first CMOS inverter configured to receive a first power supply signal and a first input signal. The transmitting and receiving circuit may include a first calculation amplifier including a non-inverted input terminal connected to an output terminal of the first CMOS inverter, and a first resistor connected between the output terminal of the first calculation amplifier and a first node. The output terminal of the first calculation amplifier and an inverted input terminal of the first calculation amplifier may be connected to each other. A first output signal may have a level smaller than that of the first input signal and may be output to the first node.

公开(公告)号：US20150100838A1

公开(公告)日：2015-04-09

申请号：US14341856

申请日：2014-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hyun BAEK ,  Jae Moo CHOI ,  Jae Hee HAN ,  In Su YANG ,  Hyun Soo JUNG

IPC: G11C29/56

CPC classification number: G11C29/56004

Abstract: A memory test device for testing a memory device is provided. The memory test device includes a sequencer configured to output first and second sequencer outputs that are different from each other in response to a sequencer input. A first pattern generator is configured to output a first test pattern according to the first sequencer output. A second pattern generator is configured to output a second test pattern according to the second sequencer output. A selector is coupled to the first and second pattern generators and configured to output write data according to the first test pattern and the second test pattern.

Abstract translation: 提供了一种用于测试存储器件的存储器测试装置。 存储器测试装置包括定序器，其被配置为响应于定序器输入而输出彼此不同的第一和第二定序器输出。 第一模式发生器被配置为根据第一定序器输出输出第一测试模式。 第二模式发生器被配置为根据第二定序器输出输出第二测试模式。 选择器耦合到第一和第二图案发生器并且被配置为根据第一测试图案和第二测试图案来输出写入数据。