公开(公告)号：US10352997B2

公开(公告)日：2019-07-16

申请号：US16053429

申请日：2018-08-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kang-Yeop Choo ,  Hyun-Ik Kim ,  Won-Seok Kim ,  Jung-Ho Kim ,  Ji-Hyun Kim ,  Tae-Ik Kim

IPC: G01R31/317

Abstract: A clock jitter measurement circuit includes: an internal signal generator configured to generate a single pulse signal and an internal clock signal which are both synchronized with an input clock signal received by the clock jitter measurement circuit, a plurality of edge delay cells serially connected to each other and configured to generate a plurality of edge detection signals respectively corresponding to a plurality of delay edges obtained by delaying an edge of the internal clock signal, a plurality of latch circuits configured to latch the single pulse signal in synchronization with the plurality of edge detection signals and output a plurality of sample signals, and a count sub-circuit configured to count a number of activated sample signals of the plurality of sample signals and output a count value based on the counted number of activated sample signals.