公开(公告)号：US11145601B2

公开(公告)日：2021-10-12

申请号：US16430630

申请日：2019-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoon Sung Kim ,  Yun Hee Kim ,  Byung Moon Bae ,  Hyun Su Sim ,  Jun Ho Yoon ,  Jung Ho Choi

IPC: H01L23/544 ,  H01L23/31 ,  H01L23/29

Abstract: A semiconductor chip including an alignment pattern is provided. The semiconductor chip includes a substrate associated with a main chip region of a semiconductor wafer and including a scribe lane. A lower interlayer insulating layer is disposed on the substrate, a low-K layer including dummy metal patterns is disposed on the lower interlayer insulating layer, an alignment pattern is disposed on the low-K layer, and a passivation layer covers the alignment pattern.

公开(公告)号：US10886234B2

公开(公告)日：2021-01-05

申请号：US16534051

申请日：2019-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Ho Yoon ,  Yoon Sung Kim ,  Yun Hee Kim ,  Byung Moon Bae ,  Hyun Su Sim ,  Jung Ho Choi

IPC: H01L23/544 ,  H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L21/782 ,  H01L21/784

Abstract: A semiconductor device is provided. The semiconductor device includes: a substrate which includes a semiconductor chip region and a scribe line region surrounding the semiconductor chip region; an insulating film arranged over the semiconductor chip region and the scribe line region on the substrate, and including a first surface, a second surface opposite to the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite to the third surface and connecting the first surface and the second surface; and an opening portion formed on the second surface of the insulating film and the fourth surface of the insulating film to expose the substrate, wherein the opening portion is formed in the scribe line region, and the first surface of the insulating film and the third surface of the insulating film do not include an opening portion which expose the substrate.

公开(公告)号：US11244911B2

公开(公告)日：2022-02-08

申请号：US16389367

申请日：2019-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoon Sung Kim ,  Yun Hee Kim ,  Byung Moon Bae ,  Hyun Su Sim ,  Jun Ho Yoon ,  Jung Ho Choi

IPC: H01L23/58

Abstract: A semiconductor chip includes a substrate including: a main chip region; and a scribe lane surrounding the main chip region; a lower interlayer insulating layer disposed on the substrate in the scribe lane; a circuit structure disposed on the lower interlayer insulating layer in the scribe lane; and a pad structure disposed on the lower interlayer insulating layer. The circuit structure and the pad structure are disposed to be spaced apart from each other in a longitudinal direction of the scribe lane.