公开(公告)号：US12299312B2

公开(公告)日：2025-05-13

申请号：US18535515

申请日：2023-12-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangoak Woo ,  Jaeho Shin ,  Hyun Jae Oh

IPC: G06F3/06

Abstract: An electronic device includes an input handling circuit, a control circuit, and a data transfer circuit. The input handling circuits receives a first request including an address from a first memory device, aligns the address with an access unit of a second memory device, requests a determination for the aligned address, and transmits a second request to the second memory device based on a determination result. The control circuit determines, based on the request, whether a duplicate address with the aligned address is present to generate the determination result and updates a bitmask based on the determination result. The data transfer circuit receives the second request from the second memory device and transfers data based on the bitmask. The bitmask includes one or more bits, each corresponding to the first request and indicating a location corresponding to the first request within an access unit of the second memory device.