Abstract:
A display drive integrated circuit includes a frame buffer, an output selector and a timing controller. The output selector selectively outputs one of image data read from the frame buffer and image data transmitted from a source external to the display drive integrated circuit. The timing controller controls output of the image data read from the frame buffer to the display panel in a self-refresh mode, and controls internal display timing to track external display timing when the display drive integrated circuit exits from the self-refresh mode to control the output selector to output the image data transmitted from the source to the display panel when the internal display timing is synchronized to the external display timing.
Abstract:
A display driving circuit includes a first bias circuit, a second bias circuit, a selector, and an output buffer. The first bias circuit generates a first bias voltage set. The second bias circuit generates a second bias voltage set. The selector selects one of the first and second bias voltage sets based on a bias selection signal. The output buffer buffers a grayscale voltage corresponding to display data and outputs the buffered grayscale voltage The output buffer is biased based on the first or second bias voltage set selected by the selector.
Abstract:
A display drive integrated circuit includes a frame buffer, an output selector and a timing controller. The output selector selectively outputs one of image data read from the frame buffer and image data transmitted from a source external to the display drive integrated circuit. The timing controller controls output of the image data read from the frame buffer to the display panel in a self-refresh mode, and controls internal display timing to track external display timing when the display drive integrated circuit exits from the self-refresh mode to control the output selector to output the image data transmitted from the source to the display panel when the internal display timing is synchronized to the external display timing.