公开(公告)号：US20240015967A1

公开(公告)日：2024-01-11

申请号：US18308393

申请日：2023-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SIYEON CHO ,  HYUNMOOK CHOI ,  JIHONG KIM

IPC: H10B43/27

CPC classification number: H10B43/27

Abstract: In a method of manufacturing a semiconductor device, an insulation layer and a first gate electrode layer are alternately and repeatedly formed on a substrate in a first direction perpendicular to an upper surface of the substrate to form a mold layer. The first gate electrode layer includes silicon doped with impurities having a first conductivity type. An opening is formed through the mold layer to expose the upper surface of the substrate. Portions of the first gate electrode layers adjacent to the opening are removed to form gaps, respectively. Horizontal channels are formed in the gaps, respectively. Each of the horizontal channels includes silicon doped with impurities having a second conductivity type. A vertical gate structure extending in the first direction is formed in the opening. A memory channel structure is formed through the mold layer to contact the upper surface of the substrate.