公开(公告)号：US20250022785A1

公开(公告)日：2025-01-16

申请号：US18410992

申请日：2024-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： PYUNGHWA HAN ,  BONG-SOO KIM ,  GYUJIN CHOI

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor chip includes a semiconductor substrate, an insulation layer positioned on the semiconductor substrate and that includes a plurality of via holes, and a bump positioned within the plurality of via holes and on the insulation layer. Portions of the bump positioned within the plurality of via holes are connected to each other.

公开(公告)号：US20240266269A1

公开(公告)日：2024-08-08

申请号：US18626388

申请日：2024-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： GYUJIN CHOI ,  JAE-EAN LEE ,  CHANGEUN JOO

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/08 ,  H01L25/105 ,  H01L2224/0603 ,  H01L2224/08235

Abstract: Disclosed is a semiconductor package device comprising a semiconductor chip including first and second chip pads on an active surface of the semiconductor chip, and a redistribution substrate on the first and second chip pads. The redistribution substrate includes first and second redistribution patterns sequentially stacked on the active surface. The first redistribution pattern includes a first via part and a first via pad part vertically overlapping the first via part. The second redistribution pattern includes a second via part and a second via pad part vertically overlapping the second via part. The first via part contacts the first chip pad. The second via part contacts the second chip pad. A length of the second via part is greater than that of the first via part.

公开(公告)号：US20210143118A1

公开(公告)日：2021-05-13

申请号：US16947093

申请日：2020-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： CHANGEUN JOO ,  GYUJIN CHOI

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31

Abstract: A semiconductor package includes a lower redistribution layer including an insulating pattern having an opening and a via in the opening; a first semiconductor chip including a chip pad, a passivation layer, and a pad bump connected to the chip pad; and a first encapsulant on the lower redistribution layer and the first semiconductor chip. The opening defines a lower surface and a side surface of the pad bump, and the via is in physical contact with the lower surface and the side surface of the pad bump.