公开(公告)号：US20240413203A1

公开(公告)日：2024-12-12

申请号：US18543414

申请日：2023-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang Min YOE ,  Ji Wang KO ,  Jae Hong CHOI ,  Jun Ho HONG ,  Dong Min KIM ,  Jeong Min CHOI

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a substrate. An active pattern is on the substrate and extends in a first horizontal direction. First to third nanosheets are sequentially stacked on the active pattern and are spaced apart from each other in a vertical direction. A gate electrode is on the active pattern and extends in a second horizontal direction. The gate electrode surrounds each of the first to third nanosheets. A source/drain region is on the active pattern on at least one side of the gate electrode. An interlayer insulating layer covers the source/drain region. A source/drain contact penetrates the interlayer insulating layer in the vertical direction and is connected to the source/drain region. At least a portion of the interlayer insulating layer is disposed between sidewalls of the source/drain contact and the source/drain region in the first horizontal direction and overlaps sidewalls of the third nanosheet along the first horizontal direction.