公开(公告)号：US10332277B2

公开(公告)日：2019-06-25

申请号：US15097309

申请日：2016-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Praveen Kumar Nelam ,  Srinivas Reddy Eregala ,  Devendran Mani

IPC: G06T9/00 ,  H04N19/00 ,  H04N19/42

Abstract: A method, executed by an encoding circuit, for selecting an optimal decimated grid includes estimating, among a plurality of decimated grids within a coded block, a weight decimation error for each of a vertical decimated grid and a horizontal decimated grid. A weight decimation error is estimated for each of remaining decimated grids among the plurality of decimated grids based on a corresponding weight decimation error among the vertical decimated grid and the horizontal decimated grid. For each of the plurality of decimated grids, an initial combined error is determined by combining the weight decimation error and a color format choice error. Two decimated grids having the least initial combined errors, among the plurality of decimated grids, are selected as optimal decimated grids.