公开(公告)号：US20250054852A1

公开(公告)日：2025-02-13

申请号：US18676836

申请日：2024-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chulho Jung

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

Abstract: A combination-type semiconductor package includes a wiring plate such as a package substrate, a redistribution structure, and an interposer or a combination thereof. A package element is mounted on the wiring plate, a delamination-preventing layer covers the package element, and a package molding layer encapsulates the package element and the delamination-preventing layer on the wiring plate. The delamination-preventing layer prevents delamination between the package element and the package molding layer.

公开(公告)号：US20240014049A1

公开(公告)日：2024-01-11

申请号：US18124255

申请日：2023-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chulho Jung ,  Jihan Ko ,  Kunsil Lee

IPC: H01L21/56 ,  H01L21/67

CPC classification number: H01L21/566 ,  H01L21/67126

Abstract: A release film for a mold process capable of minimizing defects of a semiconductor package in a semiconductor packaging process, and a method for manufacturing the release film for a mold process are provided. The release film for the mold process includes a base film and a plurality of conductive fillers located inside the base film and arranged on upper and/or lower surfaces of the base film, wherein roughness is formed by the plurality of conductive fillers on the upper and/or lower surfaces of the base film, and a conductive path is formed between the upper and lower surfaces of the base film.