公开(公告)号：US20200021245A1

公开(公告)日：2020-01-16

申请号：US16440239

申请日：2019-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-hyuk Jang ,  Shin-woong Kim ,  Young-min Kim ,  Jae-young Kim ,  Chul-ho Kim ,  Sang-wook Han

IPC: H03B5/36 ,  H03B5/06 ,  H03K5/156

Abstract: A crystal oscillator including a feedback circuit, and a reference clock generating circuit including the crystal oscillator. The crystal oscillator is configured to generate an oscillating signal based on a natural frequency of a crystal. The crystal oscillator may include: a current generating circuit connected to a first node having a first voltage and a second node having a second voltage, and configured to output a first current to the second node; a feedback circuit connected to the generating circuit via the first and second nodes and configured to adjust a level of the second voltage by controlling a level of the first voltage; and a crystal circuit connected to the second node and configured to generate the oscillating signal based on the second voltage.

公开(公告)号：US10819280B2

公开(公告)日：2020-10-27

申请号：US16440239

申请日：2019-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-hyuk Jang ,  Shin-woong Kim ,  Young-min Kim ,  Jae-young Kim ,  Chul-ho Kim ,  Sang-wook Han

IPC: H03B5/36 ,  G04F5/06 ,  H03K3/354 ,  H03K5/156 ,  H03B5/06

Abstract: A crystal oscillator including a feedback circuit, and a reference clock generating circuit including the crystal oscillator. The crystal oscillator is configured to generate an oscillating signal based on a natural frequency of a crystal. The crystal oscillator may include: a current generating circuit connected to a first node having a first voltage and a second node having a second voltage, and configured to output a first current to the second node; a feedback circuit connected to the generating circuit via the first and second nodes and configured to adjust a level of the second voltage by controlling a level of the first voltage; and a crystal circuit connected to the second node and configured to generate the oscillating signal based on the second voltage.

公开(公告)号：US11003143B2

公开(公告)日：2021-05-11

申请号：US16818276

申请日：2020-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shin-woong Kim ,  Jae-young Kim ,  Chul-ho Kim ,  Jae-hyuk Jang ,  Sang-wook Han

IPC: G04F10/00 ,  H04L7/00 ,  H03L7/089 ,  H03L7/08 ,  H04B17/14

Abstract: Provided is clock signal generator configured to generate a target output clock signal based on a reference clock signal, the clock signal generator includes a digital-to-time converter (DTC) configured to delay a reference clock signal based on an input code to generate a delay clock signal, and output the delay clock signal, a DTC controller configured to determine an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and generate the input code based on the initial gain value, and a phase locked loop configured to generate the target output clock signal based on the delay clock signal and a division clock signal of the previously generated output clock signal, the target output clock signal being locked to the delay clock signal.

公开(公告)号：US20200218203A1

公开(公告)日：2020-07-09

申请号：US16818276

申请日：2020-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shin-woong Kim ,  Jae-young Kim ,  Chul-ho Kim ,  Jae-hyuk Jang ,  Sang-wook Han

IPC: G04F10/00 ,  H04B17/14 ,  H03L7/08 ,  H03L7/089 ,  H04L7/00

Abstract: Provided is clock signal generator configured to generate a target output clock signal based on a reference clock signal, the clock signal generator includes a digital-to-time converter (DTC) configured to delay a reference clock signal based on an input code to generate a delay clock signal, and output the delay clock signal, a DTC controller configured to determine an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and generate the input code based on the initial gain value, and a phase locked loop configured to generate the target output clock signal based on the delay clock signal and a division clock signal of the previously generated output clock signal, the target output clock signal being locked to the delay clock signal.

公开(公告)号：US10606217B2

公开(公告)日：2020-03-31

申请号：US16374236

申请日：2019-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shin-woong Kim ,  Jae-young Kim ,  Chul-ho Kim ,  Jae-hyuk Jang ,  Sang-wook Han

IPC: H04L7/00 ,  H03L7/089 ,  H03L7/08 ,  G04F10/00 ,  H04B17/14

Abstract: Provided is clock signal generator configured to generate a target output clock signal based on a reference clock signal, the clock signal generator includes a digital-to-time converter (DTC) configured to delay a reference clock signal based on an input code to generate a delay clock signal, and output the delay clock signal, a DTC controller configured to determine an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and generate the input code based on the initial gain value, and a phase locked loop configured to generate the target output clock signal based on the delay clock signal and a division clock signal of the previously generated output clock signal, the target output clock signal being locked to the delay clock signal.