公开(公告)号：US20210183677A1

公开(公告)日：2021-06-17

申请号：US17007433

申请日：2020-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyujin CHOI ,  Changeun JOO

IPC: H01L21/68 ,  H01L21/66 ,  H01L21/56 ,  H01L23/00 ,  H01L21/768 ,  H01L21/48

Abstract: In a method of manufacturing a semiconductor package, a plurality of semiconductor chips are encapsulated in a carrier to provide encapsulated semiconductor chips. A first surface of the encapsulated semiconductor chips includes chip pads exposed from a first surface of the carrier. An alignment error of each of the semiconductor chips with respect to the carrier is measured. A redistribution wiring structure may be formed on the first surface of the carrier. Correction values for each layer of the redistribution wiring structure may be reflected while forming the redistribution wiring structure in order to correct the alignment error while forming the redistribution wiring structure. The redistribution wiring structure may have redistribution wirings electrically connected to the chip pads on the first surface of the carrier. Outer connection members may be formed on the redistribution wiring structure and may be configured to be electrically connected to the outermost redistribution wirings.

公开(公告)号：US20220328415A1

公开(公告)日：2022-10-13

申请号：US17849938

申请日：2022-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changeun JOO ,  Gyujin CHOI

IPC: H01L23/538 ,  H01L23/498

Abstract: A semiconductor package includes a core substrate having a through hole, a first molding member at least partially filling the through hole and covering an upper surface of the core substrate, the first molding member having a cavity within the through hole, a first semiconductor chip on the first molding member on the upper surface of the core substrate, a second semiconductor chip arranged within the cavity, a second molding member on the first molding member and covering the first semiconductor chip, a third molding member filling the cavity and covering the lower surface of the core substrate; first redistribution wirings on the second molding member and electrically connecting first chip pads of the first semiconductor chip and core connection wirings of the core substrate; and second redistribution wirings on the third molding member and electrically connecting second chip pads of the second semiconductor chip and the core connection wirings.

公开(公告)号：US20210265274A1

公开(公告)日：2021-08-26

申请号：US17032210

申请日：2020-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changeun JOO ,  Gyujin CHOI

IPC: H01L23/538 ,  H01L23/498

Abstract: A semiconductor package includes a core substrate having a through hole, a first molding member at least partially filling the through hole and covering an upper surface of the core substrate, the first molding member having a cavity within the through hole, a first semiconductor chip on the first molding member on the upper surface of the core substrate, a second semiconductor chip arranged within the cavity, a second molding member on the first molding member and covering the first semiconductor chip, a third molding member filling the cavity and covering the lower surface of the core substrate; first redistribution wirings on the second molding member and electrically connecting first chip pads of the first semiconductor chip and core connection wirings of the core substrate; and second redistribution wirings on the third molding member and electrically connecting second chip pads of the second semiconductor chip and the core connection wirings.

公开(公告)号：US20220165693A1

公开(公告)日：2022-05-26

申请号：US17343992

申请日：2021-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeean LEE ,  Changeun JOO ,  Gyujin CHOI

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor package including a semiconductor chip; a lower redistribution layer on a lower surface of the semiconductor chip; a lower passivation layer on a lower surface of the lower redistribution layer; a UBM pad on the lower passivation layer and including an upper pad and a lower pad connected to the upper pad, the upper pad having a greater horizontal length at an upper surface thereof than a horizontal length at a lower surface thereof; a seed layer between the lower passivation layer and the UBM pad; and an external connecting terminal on a lower surface of the UBM pad, wherein the seed layer includes a first seed part covering a side surface of the upper pad, a second seed part covering a portion of the lower surface of the upper pad, and a third seed part covering a portion of a side surface of the lower pad.

公开(公告)号：US20200273817A1

公开(公告)日：2020-08-27

申请号：US16703239

申请日：2019-12-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyujin CHOI ,  Sunghoan KIM ,  Changeun JOO ,  Chilwoo KWON ,  Youngkyu LIM ,  Sunguk LEE

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

Abstract: The method of manufacturing a connection structure of a semiconductor chip includes: preparing a semiconductor chip having a first surface having a connection pad disposed thereon and a second surface opposing the first surface and including a passivation layer disposed on the first surface and covering the connection pad; forming an insulating layer on the first surface of the semiconductor chip, the insulating layer covering at least a portion of the passivation layer; forming a via hole penetrating through the insulating layer to expose at least a portion of the passivation layer; exposing at least a portion of the connection pad by removing the passivation layer exposed by the via hole; forming a redistribution via by filling the via hole with a conductive material; and forming a redistribution layer on the redistribution via and the insulating layer.