公开(公告)号：US10185798B2

公开(公告)日：2019-01-22

申请号：US15343860

申请日：2016-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo Jin Kim ,  Su Hyeon Kim ,  Azmat Raheel ,  Chul Hong Park

IPC: G06F17/50 ,  H01L29/423 ,  H01L27/02 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06

Abstract: A layout design system, semiconductor device using the layout design system, and fabricating method thereof are provided. The fabricating method of a semiconductor device includes loading a first layout, wherein the first layout comprises a first active region and a first dummy region, and the first active region comprises a fin-type pattern design having a first width, generating a second layout by substituting the fin-type pattern design with a nanowire structure design and forming a nanowire structure by using the second layout, wherein the second layout comprises a second active region in the same size as the first active region, and a second dummy region in the same size as the first dummy region, the nanowire structure design has a second width greater than the first width, and the nanowire structure comprises a first nanowire extending in a first direction, a second nanowire extending in the first direction and being formed on the first nanowire at a spacing apart from the first nanowire, a gate electrode surrounding a periphery of the first nanowire and extending in a second direction of intersecting with the first direction, a gate spacer being formed on a sidewall of the gate electrode and comprising an inner sidewall and an outer sidewall facing each other, the inner sidewall of the gate spacer facing a side surface of the gate electrode, and a source/drain epitaxial layer on at least one side of the gate electrode and being connected to the first nanowire.

公开(公告)号：US20230361036A1

公开(公告)日：2023-11-09

申请号：US18140356

申请日：2023-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byung Ju KANG ,  Kwan Young Chun ,  Ji Wook Kwon ,  Chul Hong Park ,  Azmat Raheel ,  Suhyeong Choi

IPC: H01L23/528 ,  H01L23/48

CPC classification number: H01L23/5286 ,  H01L23/481

Abstract: A semiconductor device includes a substrate including a first side and a second side opposite to the first side, a first power rail and a second power rail provided on the first side of the substrate, the first power rail and the second power rail extending in a first direction and being separated in a second direction, a first active region and a second active region provided on the first side of the substrate, the first active region and the second active region being defined by an element separation film between the first power rail and the second power rail and being separated in the second direction, a power delivery network provided on the second side of the substrate, and a first power through via penetrating the element separation film and the substrate, the first power through via connecting the power delivery network and the first power rail.