公开(公告)号：US20150049103A1

公开(公告)日：2015-02-19

申请号：US14526692

申请日：2014-10-29

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Masayuki KUMETA ,  Ryo ISHII ,  Kazuhiro MATSUMOTO ,  Shinji YAMASHITA ,  Ansu LEE

IPC: G09G5/39

CPC classification number: G09G5/39 ,  G09G3/20 ,  G09G5/005 ,  G09G2310/0224 ,  G09G2310/0235 ,  G09G2310/08 ,  G09G2360/12 ,  G09G2360/18

Abstract: A control circuit for a frame memory includes a divider, a frame memory, a read control circuit, and a write control circuit. The divider divides image data into subfield data according to a plurality of subfields, where the image data is provided in synchronization with a first synchronization signal and in a unit of a frame. The frame memory has a plurality of blocks to store the subfield data. The read control circuit sequentially reads the subfield data from the blocks in synchronization with a second synchronization signal. The write control circuit writes new data to a first block before data written in a second block is read, and after data written in the first block is read by the read control circuit. The second synchronization signal may have a same cycle as the first synchronization signal and may be delayed by a preset delay time.

Abstract translation: 用于帧存储器的控制电路包括分频器，帧存储器，读控制电路和写控制电路。 分配器根据多个子场将图像数据分割成子场数据，其中图像数据与第一同步信号同步地以帧为单位提供。 帧存储器具有存储子场数据的多个块。 读取控制电路与第二同步信号同步地从块中顺序地读取子场数据。 写入控制电路在读取写入第二块中的数据之前并且在读取控制电路读取写入第一块的数据之后，将新数据写入第一块。 第二同步信号可以具有与第一同步信号相同的周期，并且可以延迟预设的延迟时间。