Abstract:
A display device includes a display unit which includes pixels and displays an image, a data driver which supplies a data signal to the pixels, and a timing controller which controls the data driver using a timing control signal. Here, the timing control signal may include a vertical synchronization signal for defining a frame period and a data enable signal for defining a display period during which an image is displayed and a blank period during which an image is not displayed. Here, lengths of blank periods may be equal to each other in a first driving mode in which the vertical synchronization signal is supplied to the timing controller in a constant cycle and in a second driving mode in which the vertical synchronization signal is supplied in different cycles.
Abstract:
A pixel includes a switching transistor connected to a data line, a first circuit to control compensation of a first driving transistor, and a second circuit to control compensation of a second driving transistor. The first and second circuits are connected to the switching transistor. The first and second transistors are connected to respective organic light emitting diodes of a same pixel. Compensation of the first and second driving transistors is based on respective first and second subscan signals, which overlap periods of corresponding common scan signals to be received by the switching transistor.