公开(公告)号：US08963118B2

公开(公告)日：2015-02-24

申请号：US13388294

申请日：2010-07-30

Applicant: Roy Somenath ,  Zhiqiang Gao

Inventor： Roy Somenath ,  Zhiqiang Gao

IPC: H01L29/22 ,  H01L29/66 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66439 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/22 ,  H01L29/775 ,  H01L29/78696

Abstract: In an embodiment, a transistor arrangement is provided. The transistor arrangement comprises a nanowire including a first nanowire region and a second nanowire region; a first gate contact disposed over the first nanowire region; an insulating region disposed over the second nanowire region; a second gate contact disposed over the insulating region; wherein the first nanowire region and the first gate contact forms a part of an enhancement mode transistor and the second nanowire region, the insulating region and the second gate contact forms a part of a depletion mode transistor. A method of forming a transistor arrangement may also be provided. Also contemplated is a transistor and a method for forming said transistor, where the transistor comprises a nanowire and a gate contact, where the gate contact is formed by directly writing the gate contact onto a region of the nanowire.

Abstract translation: 在一个实施例中，提供了晶体管布置。 晶体管布置包括包括第一纳米线区域和第二纳米线区域的纳米线; 设置在所述第一纳米线区域上的第一栅极触点; 设置在所述第二纳米线区域上的绝缘区域; 设置在所述绝缘区域上的第二栅极触点; 其中所述第一纳米线区域和所述第一栅极触点形成增强模式晶体管的一部分，并且所述第二纳米线区域，所述绝缘区域和所述第二栅极触点形成耗尽型晶体管的一部分。 还可以提供一种形成晶体管布置的方法。 晶体管和用于形成所述晶体管的方法还包括晶体管，其中晶体管包括纳米线和栅极接触，其中通过将栅极接触直接写入纳米线的区域而形成栅极接触。

公开(公告)号：US20130200332A1

公开(公告)日：2013-08-08

申请号：US13388294

申请日：2010-07-30

Applicant: Roy Somenath ,  Zhiqiang Gao

Inventor： Roy Somenath ,  Zhiqiang Gao

IPC: H01L29/66 ,  H01L29/775

CPC classification number: H01L29/66439 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/22 ,  H01L29/775 ,  H01L29/78696

Abstract: In an embodiment, a transistor arrangement is provided. The transistor arrangement comprises a nanowire including a first nanowire region and a second nanowire region; a first gate contact disposed over the first nanowire region; an insulating region disposed over the second nanowire region; a second gate contact disposed over the insulating region; wherein the first nanowire region and the first gate contact forms a part of an enhancement mode transistor and the second nanowire region, the insulating region and the second gate contact forms a part of a depletion mode transistor. A method of forming a transistor arrangement may also be provided. Also contemplated is a transistor and a method for forming said transistor, where the transistor comprises a nanowire and a gate contact, where the gate contact is formed by directly writing the gate contact onto a region of the nanowire.

Abstract translation: 在一个实施例中，提供了晶体管布置。 晶体管布置包括包括第一纳米线区域和第二纳米线区域的纳米线; 设置在所述第一纳米线区域上的第一栅极触点; 设置在所述第二纳米线区域上的绝缘区域; 设置在所述绝缘区域上的第二栅极触点; 其中所述第一纳米线区域和所述第一栅极触点形成增强模式晶体管的一部分，并且所述第二纳米线区域，所述绝缘区域和所述第二栅极触点形成耗尽型晶体管的一部分。 还可以提供一种形成晶体管布置的方法。 晶体管和用于形成所述晶体管的方法还包括晶体管，其中晶体管包括纳米线和栅极接触，其中通过将栅极接触直接写入纳米线的区域而形成栅极接触。