INQUIRER-SIDE CIRCUIT CAPABLE OF OPERATING IN ASYMMETRY DATA MODE

    公开(公告)号:US20240195450A1

    公开(公告)日:2024-06-13

    申请号:US18528163

    申请日:2023-12-04

    IPC分类号: H04B1/40 H04B3/23

    CPC分类号: H04B1/40 H04B3/23

    摘要: An inquirer-side circuit of an automotive Ethernet system includes: a hybrid circuit arranged to operably couple with an MDI circuit to conduct data communication with a respondent-side circuit; a transmitting circuit coupled with a hybrid circuit and arranged to operably generate and provide a transmission signal to the hybrid circuit; a receiving circuit coupled with the hybrid circuit and arranged to operably receive and parse a received signal transmitted from the hybrid circuit to generate a data signal; a processing circuit coupled with the receiving circuit and arranged to operably process the data signal; a physical coding sublayer circuit coupled with the processing circuit and arranged to operably conduct a physical coding operation according to the instruction of the processing circuit to control the operations of the transmitting circuit; and an echo cancellation circuit coupled between the transmitting circuit and the receiving circuit.

    INQUIRER-SIDE CIRCUIT SUPPORTING ASYMMETRY DATA MODE

    公开(公告)号:US20240195449A1

    公开(公告)日:2024-06-13

    申请号:US18527684

    申请日:2023-12-04

    IPC分类号: H04B1/40 H04B3/23

    CPC分类号: H04B1/40 H04B3/23

    摘要: An inquirer-side circuit of an automotive Ethernet system includes: a hybrid circuit arranged to operably conduct data communication with a respondent-side circuit through an MDI circuit; a transmitting circuit coupled with a hybrid circuit and arranged to operably generate and provide a transmission signal to the hybrid circuit; a receiving circuit coupled with the hybrid circuit and arranged to operably receive and parse a received signal transmitted from the hybrid circuit to generate a data signal; a processing circuit coupled with the receiving circuit and arranged to operably process the data signal; a physical coding sublayer circuit coupled with the processing circuit and arranged to operably conduct a physical coding operation to control the operations of the transmitting circuit; and an echo cancellation circuit coupled between the transmitting circuit and the receiving circuit, and arranged to operably generate an echo cancellation signal.