Abstract:
This disclosure describes efficient transformation techniques that can be used in video coding. In particular, intermediate results of computations associated with transformation of a first block of video data are reused in the transformation of a second block of video data. The techniques may be used during a motion estimation process in which video blocks of a search space are transformed, but this disclosure is not necessarily limited in this respect. Pipelining techniques may be used to accelerate the efficient transformation techniques, and transposition memories can be implemented to facilitate efficient pipelining.
Abstract:
This disclosure describes efficient transformation techniques that can be used in video coding. In particular, intermediate results of computations associated with transformation of a first block of video data are reused in the transformation of a second block of video data. The techniques may be used during a motion estimation process in which video blocks of a search space are transformed, but this disclosure is not necessarily limited in this respect. Pipelining techniques may be used to accelerate the efficient transformation techniques, and transposition memories can be implemented to facilitate efficient pipelining.
Abstract:
Efficient memory fetching techniques are described that can improve data fetching during a motion compensation decoding process. The techniques propose several different memory fetching modes that may be very efficient in different scenarios of the motion compensation decoding process. A motion compensator may a particular memory fetch mode from a plurality of possible modes on a case-by-case basis for the memory fetches associated with a motion compensation decoding process of a macroblock. The techniques described herein may be particularly useful when fractional interpolation to sub-integer pixels is used in the inter-frame compression.
Abstract:
This disclosure describes efficient memory fetching techniques that can improve data fetching during a motion compensation decoding process. The techniques propose several different memory fetching modes that may be very efficient in different scenarios of the motion compensation decoding process. In some embodiments, a motion compensator selects a particular memory fetches associated with a motion compensation decoding process of a macroblock. The techniques described herein may be particularly useful when fractional interpolation to sub-integer pixels is used in the inter-frame compression.
Abstract:
This disclosure describes techniques that make use of a waveform fetch unit that operates to retrieve waveform samples on behalf of each of a plurality of hardware processing elements that operate simultaneously to service various audio synthesis parameters generated from one or more audio files, such as musical instrument digital interface (MIDI) files. In one example, a method comprises receiving a request for a waveform sample from an audio processing element, and servicing the request by calculating a waveform sample number for the requested waveform sample based on a phase increment contained in the request and an audio synthesis parameter control word associated with the requested waveform sample, retrieving the waveform sample from a local cache using the waveform sample number, and sending the retrieved waveform sample to the requesting audio processing element.
Abstract:
The disclosure relates to systems, methods and apparatus to convert speech to text and vice versa. One apparatus comprises a vocoder, a speech to text conversion engine, a text to speech conversion engine, and a user interface. The vocoder is operable to convert speech signals into packets and convert packets into speech signals. The speech to text conversion engine is operable to convert speech to text. The text to speech conversion engine is operable to convert text to speech. The user interface is operable to receive a user selection of a mode from among a plurality of modes, wherein a first mode enables the speech to text conversion engine, a second mode enables the text to speech conversion engine, and a third mode enables the speech to text conversion engine and the text to speech conversion engine.
Abstract:
This disclosure describes techniques that make use of a plurality of hardware elements that operate simultaneously to service synthesis parameters generated from one or more audio files, such as musical instrument digital interface (MIDI) files. In one example, a method comprises storing audio synthesis parameters generated for one or more audio files of an audio frame, processing a first audio synthesis parameter using a first audio processing element of a hardware unit to generate first audio information, processing a second audio synthesis parameter using a second audio processing element of the hardware unit to generate second audio information, and generating audio samples for the audio frame based at least in part on a combination of the first and second audio information.
Abstract:
This disclosure describes techniques for processing audio files that comply with the musical instrument digital interface (MIDI) format. In particular, various tasks associated with MIDI file processing are delegated between software operating on a general purpose processor, firmware associated with a digital signal processor (DSP), and dedicated hardware that is specifically designed for MIDI file processing. Alternatively, a multi-threaded DSP may be used instead of a general purpose processor and the DSP. In one aspect, this disclosure provides a method comprising parsing MIDI files and scheduling MIDI events associated with the MIDI files using a first process, processing the MIDI events using a second process to generate MIDI synthesis parameters, and generating audio samples using a hardware unit based on the synthesis parameters.
Abstract:
This disclosure describes an organizational scheme for memory that is useful for image processing. A memory controller architecture is also described, which takes advantage of the organizational scheme. The organizational scheme and controller architecture is particularly useful for high performance, high quality image processing of images that form a video sequence, but may also be applied in other image processing settings. The described techniques and organizational structure of the memory also allows the memory to be shared for other storage applications of a video device.
Abstract:
A decoder for motion-picture-experts group (MPEG-4) video detects start codes at the beginning of video object planes (VOP) and resync markers at the start of each video packet (VP) in the VOP. When an error occurs in the bitstream, a parser searched for a next start code or resync marker to find the start of the next video packet. A partial match of the unique start-code bit sequence signals a fuzzy match, allowing the VOP header and data to be decoded even when bit errors occur in the VOP start code. A fuzzy match of the shorter resync marker can also be enabled. Fuzzy matching of VOP start codes and resync markers allows for faster recovery from corrupted bitstreams such as those transmitted over wireless networks.