公开(公告)号：US20240345762A1

公开(公告)日：2024-10-17

申请号：US18298484

申请日：2023-04-11

Applicant: QUALCOMM Incorporated

Inventor： Sravani DEVINENI ,  Sai Praneeth SREERAM ,  Madhu Yashwanth BOENAPALLI ,  Surendra PARAVADA

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods that may be performed by a universal flash storage (UFS) system of a computing device for updating logical-to-physical (L2P) address mapping tables. Various embodiments may include enabling a device control mode (DCM) of host performance booster (HPB) based on a flush of a writebooster buffer to a normal storage of a UFS device of the UFS system, and updating an L2P address mapping table at a host device of the UFS system while DCM is enabled based on the flush of the writebooster buffer to the normal storage. Some embodiments may include generating a signal having an indicator of a UFS protocol information unit configured to indicate a change in an HPB mode at the UFS device based on the flush of the writebooster buffer to the normal storage, and sending the signal from the UFS device to the host device.

公开(公告)号：US20240378166A1

公开(公告)日：2024-11-14

申请号：US18314676

申请日：2023-05-09

Applicant: QUALCOMM INCORPORATED

Inventor： Madhu Yashwanth BOENAPALLI ,  Kaustub Naidu PAILA RAM ,  Sravani DEVINENI ,  Sai Praneeth SREERAM ,  Vinod KUMAR KURUMA ,  Rajendra Varma PUSAPATI ,  Surendra PARAVADA

IPC: G06F13/42

Abstract: A Peripheral Component Interconnect Express (PCIe) system is configured to determine when the frequency of link speed switching needed to service incoming and upcoming client requests is too high. The system is also configured to determine a modest link speed to be used to service incoming and upcoming client requests in cases where the link speed switching that will be needed is too high and causes the incoming and upcoming client requests to be serviced at the modest link speed instead of at the link speeds associated with the predefined BWs of the clients. By doing this when the frequency of link speed switching needed is too high, the PCIe system achieves better throughput while also reducing power consumption.