公开(公告)号：US10318436B2

公开(公告)日：2019-06-11

申请号：US15658819

申请日：2017-07-25

Applicant: QUALCOMM Incorporated

Inventor： William McAvoy ,  Brian Stempel ,  Spencer Williams ,  Robert Douglas Clancy ,  Michael Scott McIlvaine ,  Thomas Philip Speier

IPC: G06F12/00 ,  G06F12/1045 ,  G06F12/0891 ,  G06F12/0895 ,  G06F13/00 ,  G06F13/28

Abstract: A translation lookaside buffer (TLB) index valid bit is set in a first line of a virtually indexed, virtually tagged (VIVT) cache. The first line of the VIVT cache is associated with a first TLB entry which stores a virtual address to physical address translation for the first cache line. The TLB index valid bit of the first line is cleared upon determining that the translation is no longer stored in the first TLB entry. An indication of a received invalidation instruction is stored. When a context synchronization instruction is received, the first line of the VIVT cache is cleared based on the TLB index valid bit being cleared and the stored indication of the invalidate instruction.