公开(公告)号：US20250061181A1

公开(公告)日：2025-02-20

申请号：US18452209

申请日：2023-08-18

Applicant: QUALCOMM Incorporated

Inventor： Rengarajan RAGAVAN ,  Changjian GAO ,  Samar ASBE ,  Shivaprasad HONGAL ,  Denis POCHUEV ,  Richard Wesley BASS ,  Priyanka DOSI

IPC: G06F21/33 ,  G06F21/57 ,  G06F21/64

Abstract: Systems and techniques are provided for establishing a connection. For instance, a process may include receiving, by a first root of trust (C-ROT) of a first chiplet of a plurality of chiplets from a second C-RoT of a second chiplet, a second certificate along with security state information and debug information for the second chiplet; authenticating a security state and a debug state of the second chiplet based on the security state information and the debug information; authenticating the second certificate; and establishing a security boundary with the second chiplet.

公开(公告)号：US20250097019A1

公开(公告)日：2025-03-20

申请号：US18468666

申请日：2023-09-15

Applicant: QUALCOMM Incorporated

Inventor： Rengarajan RAGAVAN ,  Arun MENON ,  Samar ASBE ,  Aseem BRAHMA ,  Shivaprasad HONGAL ,  Changjian GAO ,  Denis POCHUEV

IPC: H04L9/08 ,  G06F21/72

Abstract: Systems and techniques are provided for establishing a connection. For instance, a process may include receiving, at a first chiplet root of trust (C-ROT) of a first chiplet of a plurality of chiplets, a request for a cryptographic key; generating, by the first C-ROT, the cryptographic key; wrapping, by the first C-ROT, the cryptographic key using a wrapping key to generate a wrapped cryptographic key; outputting, by the first C-ROT, the wrapped cryptographic key; receiving the wrapped cryptographic key at a second C-ROT of a second chiplet of the plurality of chiplets; unwrapping, by the second C-ROT, the wrapped cryptographic key using the wrapping key; and performing, by the second C-ROT, an operation based on the cryptographic key.

公开(公告)号：US20220206559A1

公开(公告)日：2022-06-30

申请号：US17136175

申请日：2020-12-29

Applicant: QUALCOMM Incorporated

Inventor： Bharat Kumar RANGARAJAN ,  Rajesh ARIMILLI ,  Rengarajan RAGAVAN

IPC: G06F1/3237 ,  G06F21/74 ,  G06F3/06

Abstract: Various embodiments include methods and devices for system on chip infrastructure of system on chip infrastructure secure memory access and power management. Some embodiments, include determining whether a processor is performing a secure memory access transaction, and gating a clock signal from being transmitted to a secure portion of a memory in response to determining that the processor is not performing a secure memory access transaction. Some embodiments include determining whether any processor is operating in a secure mode, and transmitting a retention signal to the secure portion of the memory in response to determining that no processor is operating in a secure mode. The retention signal may be configured to set a retention state for the secure portion of the memory.