公开(公告)号：US10551896B2

公开(公告)日：2020-02-04

申请号：US15814361

申请日：2017-11-15

Applicant: QUALCOMM Incorporated

Inventor： Shivam Priyadarshi ,  Anil Krishna ,  Raguram Damodaran ,  Jeffrey Todd Bridges ,  Ryan Wells ,  Norman Gargash ,  Rodney Wayne Smith

IPC: G06F1/32 ,  G06F1/3228 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296

Abstract: The disclosure generally relates to dynamic clock and voltage scaling (DCVS) based on program phase. For example, during each program phase, a first hardware counter may count each cycle where a dispatch stall occurs and an oldest instruction in a load queue is a last-level cache miss, a second hardware counter may count total cycles, and a third hardware counter may count committed instructions. Accordingly, a software/firmware mechanism may read the various hardware counters once the committed instruction counter reaches a threshold value and divide a value of the first hardware counter by a value of the second hardware counter to measure a stall fraction during a current program execution phase. The measured stall fraction can then be used to predict a stall fraction in a next program execution phase such that optimal voltage and frequency settings can be applied in the next phase based on the predicted stall fraction.

公开(公告)号：US09851774B2

公开(公告)日：2017-12-26

申请号：US14986738

申请日：2016-01-04

Applicant: QUALCOMM Incorporated

Inventor： Shivam Priyadarshi ,  Anil Krishna ,  Raguram Damodaran ,  Jeffrey Todd Bridges ,  Ryan Wells ,  Norman Gargash ,  Rodney Wayne Smith

IPC: G06F1/32

CPC classification number: G06F1/3228 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: The disclosure generally relates to dynamic clock and voltage scaling (DCVS) based on program phase. For example, during each program phase, a first hardware counter may count each cycle where a dispatch stall occurs and an oldest instruction in a load queue is a last-level cache miss, a second hardware counter may count total cycles, and a third hardware counter may count committed instructions. Accordingly, a software/firmware mechanism may read the various hardware counters once the committed instruction counter reaches a threshold value and divide a value of the first hardware counter by a value of the second hardware counter to measure a stall fraction during a current program execution phase. The measured stall fraction can then be used to predict a stall fraction in a next program execution phase such that optimal voltage and frequency settings can be applied in the next phase based on the predicted stall fraction.

公开(公告)号：US20170192484A1

公开(公告)日：2017-07-06

申请号：US14986738

申请日：2016-01-04

Applicant: QUALCOMM Incorporated

Inventor： Shivam Priyadarshi ,  Anil Krishna ,  Raguram Damodaran ,  Jeffrey Todd Bridges ,  Ryan Wells ,  Norman Gargash ,  Rodney Wayne Smith

IPC: G06F1/32

CPC classification number: G06F1/3228 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: The disclosure generally relates to dynamic clock and voltage scaling (DCVS) based on program phase. For example, during each program phase, a first hardware counter may count each cycle where a dispatch stall occurs and an oldest instruction in a load queue is a last-level cache miss, a second hardware counter may count total cycles, and a third hardware counter may count committed instructions. Accordingly, a software/firmware mechanism may read the various hardware counters once the committed instruction counter reaches a threshold value and divide a value of the first hardware counter by a value of the second hardware counter to measure a stall fraction during a current program execution phase. The measured stall fraction can then be used to predict a stall fraction in a next program execution phase such that optimal voltage and frequency settings can be applied in the next phase based on the predicted stall fraction.