公开(公告)号：US20190065060A1

公开(公告)日：2019-02-28

申请号：US15688191

申请日：2017-08-28

Applicant: QUALCOMM Incorporated

Inventor： Anil Krishna ,  Gregory Michael Wright ,  Yongseok Yi ,  Matthew Gilbert ,  Vignyan Reddy Kothinti Naresh

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0802

Abstract: Caching instruction block header data in block architecture processor-based systems is disclosed. In one aspect, a computer processor device, based on a block architecture, provides an instruction block header cache dedicated to caching instruction block header data. Upon a subsequent fetch of an instruction block, cached instruction block header data may be retrieved from the instruction block header cache (if present) and used to optimize processing of the instruction block. In some aspects, the instruction block header data may include a microarchitectural block header (MBH) generated upon the first decoding of the instruction block by an MBH generation circuit. The MBH may contain static or dynamic information about the instructions within the instruction block. As non-limiting examples, the information may include data relating to register reads and writes, load and store operations, branch information, predicate information, special instructions, and/or serial execution preferences.