公开(公告)号：US09312765B2

公开(公告)日：2016-04-12

申请号：US14179218

申请日：2014-02-12

Applicant: QUALCOMM Incorporated

Inventor： Gregory Walsh ,  Zoran Janosevic ,  Mathieu Jaloux ,  Hardik M Patel

IPC: H02M3/157 ,  H02M1/088 ,  H02M1/44 ,  H02M3/156 ,  H02M1/00

CPC classification number: H02M3/157 ,  H02M1/088 ,  H02M1/44 ,  H02M3/156 ,  H02M2001/0032 ,  H02M2001/0041 ,  Y02B70/16

Abstract: In one embodiment, a circuit comprises a sense circuit configured to sense an increase in an output voltage of a switching regulator under a light load condition. A pulse generating circuit generates a control signal to switch on and off a voltage input to the switching regulator. The pulse generating circuit reduces in a binary manner a switching frequency of the control signal under the light load condition as the sensed output voltage increases. As the output voltage rises, a clock signal is divided by two to remove every second pulse and applied to the pulse generating circuit. Further increases in the output voltage cause divisions of the clock frequency by four to remove 3 of 4 pulses so that only every fourth pulse remains. With output voltage increases, the frequency is divided by eight to remove 7 of 8 pulses so that every eighth pulse remains, and so forth.

Abstract translation: 在一个实施例中，电路包括感测电路，其被配置为感测在轻负载条件下开关调节器的输出电压的增加。 脉冲发生电路产生控制信号以接通和断开输入到开关调节器的电压。 脉冲发生电路在感测的输出电压增加时，以轻负载状态以二进制方式降低控制信号的开关频率。 当输出电压上升时，将时钟信号除以2以消除每秒脉冲并施加到脉冲发生电路。 输出电压的进一步增加会导致时钟频率分割四分之一，以消除4个脉冲中的3个，从而只剩下每四个脉冲。 随着输出电压的增加，频率被除以8以消除8个脉冲中的7个，使得每八个脉冲保持等等。

公开(公告)号：US20150229211A1

公开(公告)日：2015-08-13

申请号：US14179218

申请日：2014-02-12

Applicant: QUALCOMM Incorporated

Inventor： Gregory Walsh ,  Zoran Janosevic ,  Mathieu Jaloux ,  Hardik M. Patel

IPC: H02M3/157 ,  H02M1/088

CPC classification number: H02M3/157 ,  H02M1/088 ,  H02M1/44 ,  H02M3/156 ,  H02M2001/0032 ,  H02M2001/0041 ,  Y02B70/16

Abstract: In one embodiment, a circuit comprises a sense circuit configured to sense an increase in an output voltage of a switching regulator under a light load condition. A pulse generating circuit generates a control signal to switch on and off a voltage input to the switching regulator. The pulse generating circuit reduces in a binary manner a switching frequency of the control signal under the light load condition as the sensed output voltage increases. As the output voltage rises, a clock signal is divided by two to remove every second pulse and applied to the pulse generating circuit. Further increases in the output voltage cause divisions of the clock frequency by four to remove 3 of 4 pulses so that only every fourth pulse remains. With output voltage increases, the frequency is divided by eight to remove 7 of 8 pulses so that every eighth pulse remains, and so forth.

Abstract translation: 在一个实施例中，电路包括感测电路，其被配置为感测在轻负载条件下开关调节器的输出电压的增加。 脉冲发生电路产生控制信号以接通和断开输入到开关调节器的电压。 脉冲发生电路在感测的输出电压增加时，以轻负载状态以二进制方式降低控制信号的开关频率。 当输出电压上升时，将时钟信号除以2以消除每秒脉冲并施加到脉冲发生电路。 输出电压的进一步增加会导致时钟频率分割四分之一，以消除4个脉冲中的3个，从而只剩下每四个脉冲。 随着输出电压的增加，频率被除以8以消除8个脉冲中的7个，使得每八个脉冲保持等等。