公开(公告)号：US20230299050A1

公开(公告)日：2023-09-21

申请号：US17700329

申请日：2022-03-21

Applicant: QUALCOMM Incorporated

Inventor： Kunal Jain MANGILAL ,  Madan KRISHNAPPA

IPC: H01L25/065 ,  H01L21/66 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L22/34 ,  H01L22/12 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596

Abstract: Stacked circuits are configured to facilitate post-stacking testing. According to one example, a stacked circuit may include a first die electrically coupled to a second die through a plurality of interconnects. The first die may include a test input interface configured to receive test data signals and a source test clock signal, a test output interface configured to convey test responses, a first test signal path, at least one first die-to-die output interface configured to convey to the second die the test data signals and a low-latency clock signal received from a low-latency clock path between the test input interface and the at least one first die-to-die output interface, and at least one first die-to-die input interface configured to receive test responses and the clock signal from the second die. Other aspects, embodiments, and features are also included.