Efficient Directed Acyclic Graph Pattern Matching To Enable Code Partitioning and Execution On Heterogeneous Processor Cores
    1.
    发明申请
    Efficient Directed Acyclic Graph Pattern Matching To Enable Code Partitioning and Execution On Heterogeneous Processor Cores 有权
    有效的定向非循环图模式匹配以在异构处理器内核上启用代码分区和执行

    公开(公告)号:US20150052331A1

    公开(公告)日:2015-02-19

    申请号:US13969735

    申请日:2013-08-19

    CPC classification number: G06F9/3877 G06F8/35 G06F8/44 G06F8/451 G06F9/3885

    Abstract: Methods, devices, and systems for automatically determining how an application program may be partitioned and offloaded for execution by a general purpose applications processor and an auxiliary processor (e.g., a DSP, GPU, etc.) within a mobile device. The mobile device may determine the portions of the application code that are best suited for execution on the auxiliary processor based on pattern-matching of directed acyclic graphs (DAGS). In particular, the mobile device may identify one or more patterns in the code, particularly in a data flow graph of the code, comparing each identified code pattern to predefined graph patterns known to have a certain benefit when executed on the auxiliary processor (e.g., a DSP). The mobile device may determine the costs and/or benefits of executing the potions of code on the auxiliary processor, and may offload portions that have low costs and/or high benefits related to the auxiliary processor.

    Abstract translation: 用于自动确定应用程序如何被分割和卸载以由移动设备内的通用应用处理器和辅助处理器(例如,DSP,GPU等)执行的方法,设备和系统。 移动设备可以基于有向非循环图(DAGS)的模式匹配来确定最适合在辅助处理器上执行的应用代码的部分。 特别地,移动设备可以识别代码中的一个或多个模式,特别是在代码的数据流图中,将每个识别的代码模式与在辅助处理器上执行时已知具有一定益处的预定义图形模式进行比较(例如, 一个DSP)。 移动设备可以确定在辅助处理器上执行代码段的成本和/或益处,并且可以卸载与辅助处理器相关的低成本和/或高优点的部分。

    CONCURRENT PARSING AND PROCESSING OF SERIAL LANGUAGES
    2.
    发明申请
    CONCURRENT PARSING AND PROCESSING OF SERIAL LANGUAGES 审中-公开
    串行语言的并行处理和处理

    公开(公告)号:US20130047077A1

    公开(公告)日:2013-02-21

    申请号:US13656111

    申请日:2012-10-19

    CPC classification number: G06F17/272 G06F17/2247 G06F17/2725

    Abstract: The aspects enable a processor to concurrently execute a first serial language code embedding a second serial language code during a page load by a browser. A parser parses the first serial language code until a segment of the embedded second serial language code is encountered. The segment of embedded second serial language code is extracted for execution by an execution engine, which proceeds concurrently with speculative parsing of the first serial language code. Code generated by execution of second serial language code is evaluated to determine if it is well-formed, and partial rollback and re-parsing of the first serial language code is performed if the code is not well-formed. Concurrent parsing of first serial language code and execution of second language code, with partial roll back and reparsing when necessary, continues until the first language code has been parsed and the second serial language code has been executed.

    Abstract translation: 这些方面使得处理器能够在浏览器的页面加载期间同时执行嵌入第二串行语言代码的第一串行语言代码。 解析器解析第一个串行语言代码,直到遇到嵌入式第二个串行语言代码的一段。 提取嵌入式第二串行语言代码段以供执行引擎执行,该执行引擎与第一串行语言代码的推测性解析同时进行。 对执行第二串行语言代码生成的代码进行评估,以确定其是否格式正确,如果代码形式不正确,则执行第一个串行语言代码的部分回滚和重新解析。 同时解析第一个串行语言代码和执行第二个语言代码,必要时进行部分回滚和重新编译,直到第一个语言代码被解析并且第二个串行语言代码被执行为止。

    Dynamic address negotiation for shared memory regions in heterogenous multiprocessor systems
    3.
    发明授权
    Dynamic address negotiation for shared memory regions in heterogenous multiprocessor systems 有权
    异构多处理器系统中共享内存区域的动态地址协商

    公开(公告)号:US09311011B2

    公开(公告)日:2016-04-12

    申请号:US13961085

    申请日:2013-08-07

    CPC classification number: G06F3/0638 G06F3/0613 G06F3/0671 G06F9/544

    Abstract: Mobile computing devices may be configured to compile and execute portions of a general purpose software application in an auxiliary processor (e.g., a DSP) of a multiprocessor system by reading and writing information to a shared memory. A first process (P1) on the applications processor may request address negotiation with a second process (P2) on the auxiliary processor, obtain a first address map from a first operating system, and send the first address map to the auxiliary processor. The second process (P2) may receive the first address map, obtain a second address map from a second operating system, identify matching addresses in the first and second address maps, store the matching addresses as common virtual addresses, and send the common virtual addresses back to the applications processor. The first and second processes (i.e., P1 and P2) may each use the common virtual addresses to map physical pages to the memory.

    Abstract translation: 移动计算设备可以被配置为通过将信息读取和写入到共享存储器来编译和执行多处理器系统的辅助处理器(例如,DSP)中的通用软件应用的部分。 应用处理器上的第一进程(P1)可以在辅助处理器上请求与第二进程(P2)的地址协商,从第一操作系统获得第一地址映射,并将第一地址映射发送到辅助处理器。 第二进程(P2)可以接收第一地址映射,从第二操作系统获得第二地址映射,识别第一和第二地址映射中的匹配地址,将匹配地址存储为公共虚拟地址,并发送公共虚拟地址 回到应用处理器。 第一和第二进程(即P1和P2)可以各自使用公共虚拟地址将物理页面映射到存储器。

    Energy-Efficient Run-Time Offloading of Dynamically Generated Code in Heterogenuous Multiprocessor Systems
    4.
    发明申请
    Energy-Efficient Run-Time Offloading of Dynamically Generated Code in Heterogenuous Multiprocessor Systems 审中-公开
    在异构多处理器系统中动态生成代码的高效运行时间卸载

    公开(公告)号:US20150046679A1

    公开(公告)日:2015-02-12

    申请号:US13961122

    申请日:2013-08-07

    Abstract: Mobile computing devices may be configured to intelligently select, compile, and execute portions of a general purpose software application in an auxiliary processor (e.g., a DSP) of a multiprocessor system. A processor of the mobile device may be configured to determine whether portions of a software application are suitable for execution in an auxiliary processor, monitor operating conditions of the system, determine a historical context based on the monitoring, and determine whether the portions that were determined to suitable for execution in an auxiliary processor should be compiled for execution in the auxiliary processor based on the historical context. The processor may also be configured to continue monitoring the system, update the historical context information, and determine whether code previously compiled for execution on the auxiliary processor should be invoked or executed in the auxiliary processor based on the updated historical context information.

    Abstract translation: 移动计算设备可以被配置为在多处理器系统的辅助处理器(例如,DSP)中智能地选择,编译和执行通用软件应用的部分。 移动设备的处理器可以被配置为确定软件应用的部分是否适合于在辅助处理器中执行,监视系统的操作条件,基于监视来确定历史上下文,并且确定是否确定了部分 在辅助处理器中适合执行的编译应在基于历史上下文的辅助处理器中执行。 处理器还可以被配置为继续监视系统,更新历史上下文信息,并且确定是否应该在辅助处理器中基于更新的历史上下文信息来调用或执行在辅助处理器上执行的先前编译的代码。

    Method for controlling inlining in a code generator
    5.
    发明授权
    Method for controlling inlining in a code generator 有权
    用于控制代码生成器中的内联的方法

    公开(公告)号:US09304748B2

    公开(公告)日:2016-04-05

    申请号:US14014571

    申请日:2013-08-30

    Abstract: The various aspects leverage the novel observation that the number of call sites in code is directly correlated with the code's compile time and provide methods implemented by a compiler operating on a computing device (e.g., a smartphone) for performing inline throttling based on a projected number of call sites in the code that would exist after performing inline expansion. The various aspects enable the compiler to improve the performance of the generated code by aggressive inlining while carefully managing increases in compile time, thereby decreasing the power required to compile the code while increasing performance of the computing device. Thus, by inlining enough call sites to reduce the costs of handling calls while accounting for the costs of inlining, the various aspects provide for an effective balance of short compile times and effective code performance.

    Abstract translation: 各个方面利用新颖的观察结果,代码中的调用位置的数量与代码的编译时间直接相关,并提供由在计算设备(例如,智能电话机)上操作的编译器实现的方法,用于基于预测的数字执行内联调节 在执行内联扩展后将存在的代码中的调用网站。 各个方面使编译器能够通过积极的内联来提高生成代码的性能,同时谨慎地管理编译时间的增加,从而降低编译代码所需的功耗,同时提高计算设备的性能。 因此,通过内联足够的呼叫站点来降低处理呼叫的成本,同时考虑到内联的成本,各个方面提供了缩短编译时间和有效的代码执行的有效平衡。

    Dynamic Address Negotiation for Shared Memory Regions in Heterogeneous Muliprocessor Systems
    6.
    发明申请
    Dynamic Address Negotiation for Shared Memory Regions in Heterogeneous Muliprocessor Systems 有权
    非均匀多处理器系统中共享内存区域的动态地址协商

    公开(公告)号:US20150046661A1

    公开(公告)日:2015-02-12

    申请号:US13961085

    申请日:2013-08-07

    CPC classification number: G06F3/0638 G06F3/0613 G06F3/0671 G06F9/544

    Abstract: Mobile computing devices may be configured to compile and execute portions of a general purpose software application in an auxiliary processor (e.g., a DSP) of a multiprocessor system by reading and writing information to a shared memory. A first process (P1) on the applications processor may request address negotiation with a second process (P2) on the auxiliary processor, obtain a first address map from a first operating system, and send the first address map to the auxiliary processor. The second process (P2) may receive the first address map, obtain a second address map from a second operating system, identify matching addresses in the first and second address maps, store the matching addresses as common virtual addresses, and send the common virtual addresses back to the applications processor. The first and second processes (i.e., P1 and P2) may each use the common virtual addresses to map physical pages to the memory.

    Abstract translation: 移动计算设备可以被配置为通过将信息读取和写入到共享存储器来编译和执行多处理器系统的辅助处理器(例如,DSP)中的通用软件应用的部分。 应用处理器上的第一进程(P1)可以在辅助处理器上请求与第二进程(P2)的地址协商,从第一操作系统获得第一地址映射,并将第一地址映射发送到辅助处理器。 第二进程(P2)可以接收第一地址映射,从第二操作系统获得第二地址映射,识别第一和第二地址映射中的匹配地址,将匹配地址存储为公共虚拟地址,并发送公共虚拟地址 回到应用处理器。 第一和第二进程(即P1和P2)可以各自使用公共虚拟地址将物理页面映射到存储器。

    Efficient directed acyclic graph pattern matching to enable code partitioning and execution on heterogeneous processor cores
    7.
    发明授权
    Efficient directed acyclic graph pattern matching to enable code partitioning and execution on heterogeneous processor cores 有权
    高效的有向无环图模式匹配,以实现异构处理器内核上的代码分割和执行

    公开(公告)号:US09201659B2

    公开(公告)日:2015-12-01

    申请号:US13969735

    申请日:2013-08-19

    CPC classification number: G06F9/3877 G06F8/35 G06F8/44 G06F8/451 G06F9/3885

    Abstract: Methods, devices, and systems for automatically determining how an application program may be partitioned and offloaded for execution by a general purpose applications processor and an auxiliary processor (e.g., a DSP, GPU, etc.) within a mobile device. The mobile device may determine the portions of the application code that are best suited for execution on the auxiliary processor based on pattern-matching of directed acyclic graphs (DAGS). In particular, the mobile device may identify one or more patterns in the code, particularly in a data flow graph of the code, comparing each identified code pattern to predefined graph patterns known to have a certain benefit when executed on the auxiliary processor (e.g., a DSP). The mobile device may determine the costs and/or benefits of executing the portions of code on the auxiliary processor, and may offload portions that have low costs and/or high benefits related to the auxiliary processor.

    Abstract translation: 用于自动确定应用程序如何被分割和卸载以由移动设备内的通用应用处理器和辅助处理器(例如,DSP,GPU等)执行的方法,设备和系统。 移动设备可以基于有向非循环图(DAGS)的模式匹配来确定最适合在辅助处理器上执行的应用代码的部分。 特别地,移动设备可以识别代码中的一个或多个模式,特别是在代码的数据流图中,将每个识别的代码模式与在辅助处理器上执行时已知具有一定益处的预定义图形模式进行比较(例如, 一个DSP)。 移动设备可以确定在辅助处理器上执行代码部分的成本和/或益处,并且可以卸载与辅助处理器相关的低成本和/或高优点的部分。

    Fast, combined forwards-backwards pass global optimization framework for dynamic compilers
    8.
    发明授权
    Fast, combined forwards-backwards pass global optimization framework for dynamic compilers 有权
    快速,组合的前进后退通过动态编译器的全局优化框架

    公开(公告)号:US09176760B2

    公开(公告)日:2015-11-03

    申请号:US14034770

    申请日:2013-09-24

    CPC classification number: G06F8/447 G06F8/443 G06F9/45516

    Abstract: The various aspects provide a dynamic compilation framework that includes a machine-independent optimization module operating on a computing device and methods for optimizing code with the machine-independent optimization module using a single, combined-forwards-backwards pass of the code. In the various aspects, the machine-independent optimization module may generate a graph of nodes from the IR, optimize nodes in the graph using forwards and backwards optimizations, and propagating the forwards and backwards optimizations to nodes in a bounded subgraph recognized or defined based on the position of the node currently being optimized. In the various aspects, the machine-independent optimization module may optimize the graph by performing forwards and/or backwards optimizations during a single pass through the graph, thereby achieving an effective degree of optimization and shorter overall compile times. Thus, the various aspects may provide a global optimization framework for dynamic compilers that is faster and more efficient than existing solutions.

    Abstract translation: 各个方面提供了一个动态编译框架,其中包括一个在计算设备上运行的独立于计算机的优化模块,以及使用独立的组合后向传递代码的独立于机器的优化模块来优化代码的方法。 在各个方面,独立于机器的优化模块可以从IR生成节点图,使用向前和向后优化来优化图中的节点,并且将前向和后向优化传播到基于 当前正在优化节点的位置。 在各个方面,独立于机器的优化模块可以在单次通过图形期间执行前向和/或后向优化来优化图形,从而实现有效的优化程度和更短的整体编译时间。 因此,各个方面可以为动态编译器提供一个比现有解决方案更快更有效的全局优化框架。

    Fast, Combined Forwards-Backwards Pass Global Optimization Framework for Dynamic Compilers
    9.
    发明申请
    Fast, Combined Forwards-Backwards Pass Global Optimization Framework for Dynamic Compilers 有权
    快速,组合向前 - 向后传递动态编译器的全局优化框架

    公开(公告)号:US20150089484A1

    公开(公告)日:2015-03-26

    申请号:US14034770

    申请日:2013-09-24

    CPC classification number: G06F8/447 G06F8/443 G06F9/45516

    Abstract: The various aspects provide a dynamic compilation framework that includes a machine-independent optimization module operating on a computing device and methods for optimizing code with the machine-independent optimization module using a single, combined-forwards-backwards pass of the code. In the various aspects, the machine-independent optimization module may generate a graph of nodes from the IR, optimize nodes in the graph using forwards and backwards optimizations, and propagating the forwards and backwards optimizations to nodes in a bounded subgraph recognized or defined based on the position of the node currently being optimized. In the various aspects, the machine-independent optimization module may optimize the graph by performing forwards and/or backwards optimizations during a single pass through the graph, thereby achieving an effective degree of optimization and shorter overall compile times. Thus, the various aspects may provide a global optimization framework for dynamic compilers that is faster and more efficient than existing solutions.

    Abstract translation: 各个方面提供了一个动态编译框架,其中包括一个在计算设备上运行的独立于计算机的优化模块,以及使用独立的组合后向传递代码的独立于机器的优化模块来优化代码的方法。 在各个方面,独立于机器的优化模块可以从IR生成节点图,使用向前和向后优化来优化图中的节点,并且将前向和后向优化传播到基于 当前正在优化节点的位置。 在各个方面,独立于机器的优化模块可以在单次通过图形期间执行前向和/或后向优化来优化图形,从而实现有效的优化程度和更短的整体编译时间。 因此,各个方面可以为动态编译器提供一个比现有解决方案更快更有效的全局优化框架。

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