Machine learning-based integrated circuit test case selection for timing analysis

    公开(公告)号:US11928411B2

    公开(公告)日:2024-03-12

    申请号:US17484536

    申请日:2021-09-24

    CPC classification number: G06F30/3315 G06N3/045 G06F2119/12

    Abstract: Certain aspects of the present disclosure provide techniques for testing integrated circuit designs based on test cases selected using machine learning models. An example method generally includes receiving a plurality of test cases for an integrated circuit. An embedding data set is generated from the plurality of test cases. A respective embedding for a respective test case of the plurality of test cases generally includes a mapping of the respective test case into a multidimensional space. A plurality of test case clusters is generated based on a clustering model and the embedding data set. A plurality of critical test cases for testing the integrated circuit is selected based on the plurality of test case clusters. The integrated circuit is timed based on the plurality of critical test cases and a hard macro defining the integrated circuit.

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