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    ADAPTIVE MEMORY ERROR DETECTION AND CORRECTION
    1.
    发明公开
    ADAPTIVE MEMORY ERROR DETECTION AND CORRECTION 审中-公开

    公开(公告)号：US20230342241A1

    公开(公告)日：2023-10-26

    申请号：US17725170

    申请日：2022-04-20

    Applicant: QUALCOMM INCORPORATED

    Inventor： DEEPAK KUMAR AGARWAL ,  Kunal DESAI ,  Jimit SHAH ,  Rakesh GEHALOT

    IPC: G06F11/10

    CPC classification number: G06F11/1044

    Abstract: Error detection and correction (EDAC) logic of a memory subsystem may be monitored for error corrections, with the EDAC logic configured to use a first EDAC level. The number of error corrections made by the EDAC logic while using the first EDAC level during a time interval may be determined. The EDAC logic may be switched from using the first EDAC level to using a second EDAC level when the number of error corrections using the first EDAC level during the time interval exceeds a threshold.

    Effective DRAM Interleaving For Asymmetric Size Channels Or Ranks While Supporting Improved Partial Array Self-Refresh
    2.
    发明申请
    Effective DRAM Interleaving For Asymmetric Size Channels Or Ranks While Supporting Improved Partial Array Self-Refresh 有权

    公开(公告)号：US20220254409A1

    公开(公告)日：2022-08-11

    申请号：US17174073

    申请日：2021-02-11

    Applicant: QUALCOMM Incorporated

    Inventor： Kunal DESAI ,  Saurabh JAISWAL ,  Vikrant KUMAR ,  Swaraj SHA ,  Dharmesh PARIKH

    IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4093

    Abstract: Various embodiments include methods and devices for portion interleaving for asymmetric size memory portions. Embodiments may include determining an asymmetric memory portion assignment for an interleave unit, determining a consumed address space offset for consumed address space of a memory, modifying an address of the interleave unit using the consumed address space offset, and assigning the interleave unit to an interleave granule in the asymmetric memory portion using the modified address in a compact manner before assigning another interleave unit to another interleave granule. Embodiments may include receiving an address of memory access request in a memory, mapping the address to an interleave granule in an asymmetric memory portion, assigning consecutive interleave units to the interleave granule while the interleave granule has unused space before assigning another interleave unit to another interleave granule, and implementing the memory access request at the mapped address.

    METHOD AND SYSTEM FOR REFRESHING MEMORY OF A PORTABLE COMPUTING DEVICE
    3.
    发明公开
    METHOD AND SYSTEM FOR REFRESHING MEMORY OF A PORTABLE COMPUTING DEVICE 审中-公开

    公开(公告)号：US20230386551A1

    公开(公告)日：2023-11-30

    申请号：US18249925

    申请日：2021-10-20

    Applicant: QUALCOMM INCORPORATED

    Inventor： Pranav AGRAWAL ,  Akash SUTHAR ,  Aman CHHETRY ,  Kunal DESAI

    IPC: G11C11/406

    CPC classification number: G11C11/40618 ,  G11C11/40615

    Abstract: A kernel of an HLOS may originate one or more memory refresh requests. Each memory refresh request may have a first memory address range and a size value. A resource power manager may be coupled to the kernel and coupled to memory. The memory may have a plurality of memory ranks. The resource power manger may receive a memory refresh request from the kernel. The resource power manager may then determine if the plurality of memory ranks is either symmetrical or asymmetrical. If the memory ranks are symmetrical, then the resource power manager distributes the memory refresh request evenly and in a parallel manner across the symmetrical memory ranks. If the memory ranks are asymmetrical, then the resource power manager will then determine if the memory refresh request should be one of: a linear only memory refresh; an interleave with linear memory refresh; or an interleave only memory refresh.

    DYNAMIC DIE-TO-DIE SERIAL LANE CONFIGURATION
    5.
    发明公开
    DYNAMIC DIE-TO-DIE SERIAL LANE CONFIGURATION 审中-公开

    公开(公告)号：US20240354275A1

    公开(公告)日：2024-10-24

    申请号：US18302535

    申请日：2023-04-18

    Applicant: QUALCOMM INCORPORATED

    Inventor： Kunal DESAI ,  Deepak Kumar AGARWAL

    IPC: G06F13/42 ,  G06F11/07

    CPC classification number: G06F13/4282 ,  G06F11/0745 ,  G06F11/076

    Abstract: A die-to-die serial data link may be dynamically configured to exclude lanes associated with data errors. In a test mode, data may be transmitted from a first die to a second die over lanes of the link. In the second die, data received on the link in the test mode may be compared with an expected data pattern to detect any bit mismatches. When there are no more than a threshold number of mismatched bits, a receive path in the second die may be configured to use all of the lanes. When there are more than the threshold number of mismatched bits, a sub-group of the lanes that are not associated with mismatched bits may be determined, and the receive path in the second die may be configured to use the sub-group of lanes. In the first die, a transmit path may be configured to use the sub-group of lanes.

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