公开(公告)号：US20220181353A1

公开(公告)日：2022-06-09

申请号：US17530014

申请日：2021-11-18

Applicant: Postech Research and Business Development Foundation

Inventor： Jang-Sik LEE ,  Ik-Jyae KIM ,  Min-Kyu KIM

IPC: H01L27/11597 ,  H01L21/02 ,  H01L29/24 ,  H01L21/28 ,  H01L29/51

Abstract: A method for manufacturing a semiconductor memory device according to the inventive concept includes forming an electrode structure by alternately stacking insulation layers and electrodes on a substrate, forming a channel hole penetrating the electrode structure, and forming a vertical channel structure filling the channel hole, wherein the forming the vertical channel structure includes forming a ferroelectric layer on an inner sidewall of the channel hole, forming an oxide semiconductor layer on the ferroelectric layer, and performing an annealing process on the oxide semiconductor layer.