公开(公告)号：US20230275089A1

公开(公告)日：2023-08-31

申请号：US18143608

申请日：2023-05-05

Applicant: PixArt Imaging Inc.

Inventor： Yung-Ju WEN ,  Han-Chi LIU ,  Hsin-You KO

IPC: H01L27/092

CPC classification number: H01L27/0921

Abstract: There is provided a logic circuit capable of preventing latch-up. The conducting of a parasitic SCR is prevented by doping an additional N+ active region in the N well region of a PMOS transistor and doping an additional P+ active region in the P well region of an NMOS transistor so as to prevent the occurrence of latch-up.

公开(公告)号：US20220302112A1

公开(公告)日：2022-09-22

申请号：US17206862

申请日：2021-03-19

Applicant: PixArt Imaging Inc.

Inventor： Yung-Ju WEN ,  Han-Chi LIU ,  Hsin-You KO

IPC: H01L27/092

Abstract: There is provided a logic circuit capable of preventing latch-up. The conducting of a parasitic SCR is prevented by doping an additional N+ active region in the N well region of a PMOS transistor and doping an additional P+ active region in the P well region of an NMOS transistor so as to prevent the occurrence of latch-up.