公开(公告)号：US20230273786A1

公开(公告)日：2023-08-31

申请号：US18143609

申请日：2023-05-05

Applicant: PixArt Imaging Inc.

Inventor： Jr-Yi LI

IPC: G06F8/65 ,  G06F9/4401

CPC classification number: G06F8/65 ,  G06F9/4411

Abstract: There is provided a control chip including a microcontroller unit (MCU), a bus arbiter, a first bus, a second bus, a void hardware, a cache controller, a flash controller and a flash memory, wherein the flash memory is recorded with a firmware. When the MCU does not receive an update instruction, the bus arbiter reads, according to a function command of the MCU, a function return value associated with the function command from the flash memory via the first bus, the cache controller and the flash controller. When the MCU receives the update instruction, the bus arbiter updates the firmware in the flash memory via the second bus and the flash controller, and the void hardware actively replies a void return value associated with the function command to the MCU to replace the function return value.

公开(公告)号：US20230166180A1

公开(公告)日：2023-06-01

申请号：US17536900

申请日：2021-11-29

Applicant: PIXART IMAGING INC.

Inventor： Jr-Yi LI

IPC: A63F13/22 ,  A63F13/23 ,  A63F13/533

CPC classification number: A63F13/22 ,  A63F13/23 ,  A63F13/533 ,  G06F3/03543

Abstract: There is provided a computer system including a mouse device and a host. The mouse device receives a command script from the host to determine output data to be transmitted to the host. The output data includes, for example, at least one pressed key signal and/or a movement signal. The command script is previously recorded in the host or is determined according to raw data detected by the mouse device. The present disclosure further provides a gaming mouse.

公开(公告)号：US20220206777A1

公开(公告)日：2022-06-30

申请号：US17136480

申请日：2020-12-29

Applicant: PixArt Imaging Inc.

Inventor： Jr-Yi LI

IPC: G06F8/65 ,  G06F9/4401

Abstract: There is provided a control chip including a microcontroller unit (MCU), a bus arbiter, a first bus, a second bus, a void hardware, a cache controller, a flash controller and a flash memory, wherein the flash memory is recorded with a firmware. When the MCU does not receive an update instruction, the bus arbiter reads, according to a function command of the MCU, a function return value associated with the function command from the flash memory via the first bus, the cache controller and the flash controller. When the MCU receives the update instruction, the bus arbiter updates the firmware in the flash memory via the second bus and the flash controller, and the void hardware actively replies a void return value associated with the function command to the MCU to replace the function return value.