公开(公告)号：US11036904B2

公开(公告)日：2021-06-15

申请号：US16714583

申请日：2019-12-13

Applicant: POSTECH Research and Business Development Foundation

Inventor： Seokhyeong Kang ,  Sunmean Kim ,  Sung-Yun Lee

IPC: G06F30/327 ,  G06F30/373 ,  H03K19/0944 ,  H03K19/094

Abstract: Provided is a ternary logic synthesis method at least temporarily performed by a computer, the ternary logic synthesis method including generating a switching table with respect to pull-up and pull-down circuits using a truth table corresponding to a ternary function, converting the switching table into a sum of products (SOP) using a Quine-McCluskey algorithm, minimizing the SOP, and mapping a transistor corresponding to the SOP.