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公开(公告)号：US20220069821A1
公开(公告)日：2022-03-03
申请号：US17298917
申请日：2019-12-09
Inventor： Eun Hwan KIM , Jae-Joon KIM
IPC: H03K19/0944
Abstract: A pseudo-complementary logic network according to this embodiment includes a first logic stage including a first pull-up circuit of an N-type transistor and a first pull-down circuit and a second logic stage including a second pull-up circuit and a second pull-down circuit of an N-type transistor, wherein an output signal of the second logic stage is provided as an input of the first pull-down circuit, and the first pull-up circuit includes the second pull-down circuit.
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