公开(公告)号：US11664382B2

公开(公告)日：2023-05-30

申请号：US17354910

申请日：2021-06-22

Applicant: POSTECH Research and Business Development Foundation

Inventor： Chang-Ki Baek ,  Gayoung Kim ,  Byoung-Don Kong ,  Hyangwoo Kim

IPC: G11C11/34 ,  H01L27/102 ,  G11C11/39

CPC classification number: H01L27/1027 ,  H10B12/00 ,  G11C11/39

Abstract: A memory device includes at least one semiconductor layer having a double PN junction, and an anode and a cathode which simultaneously contact the semiconductor layer, wherein a junction between the semiconductor layer and the anode is a Schottky junction, and a junction between the semiconductor layer and the cathode is an Ohmic junction. In addition, a capacitor-less memory device includes at least one semiconductor layer including a double PN junction, a control gate which contacts the semiconductor layer, and an anode and a cathode which simultaneously contact the semiconductor layer, wherein a junction between the semiconductor layer and the anode is a Schottky junction, and a junction between the semiconductor layer and the cathode is an Ohmic junction. Methods of operating the memory device and the capacitor-less memory device are also disclosed.