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公开(公告)号：US20210209038A1
公开(公告)日：2021-07-08
申请号：US17208354
申请日：2021-03-22
Inventor： Tadashi ONO , Isao KATO , Yoshihisa INAGAKI , Shuichi OHKI
Abstract: When a part of a signal line of a first interface and a part of a signal line of a second interface share a signal line and there is a memory connected to both the interfaces, initialization of the second interface and initialization of the memory are executed in parallel following initialization of the first interface.
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