公开(公告)号：US12262563B2

公开(公告)日：2025-03-25

申请号：US17701632

申请日：2022-03-22

Applicant: Omnivision Technologies, Inc.

Inventor： Shiyu Sun ,  Yuanwei Zheng ,  Gang Chen ,  Sing-Chung Hu ,  Armin Yazdani

IPC: H10F39/18

Abstract: A pixel cell is formed on a semiconductor substrate having a front surface. The pixel cell includes a photodiode, a floating diffusion region, and a transfer gate. The photodiode is disposed in the semiconductor substrate. The floating diffusion region includes a first doped region disposed in the semiconductor substrate, wherein the first doped region extends from the front surface to a first junction depth in the semiconductor substrate. The transfer gate is configured to selectively couple the photodiode to the floating diffusion region controlling charge transfer between the photodiode and the floating diffusion region. The transfer gate includes a planar gate disposed on the front surface of the semiconductor substrate and a pair of vertical gate electrodes. Each vertical gate electrode extending a gate depth from the planar gate into the semiconductor substrate. The first junction depth is greater than the gate depth.

公开(公告)号：US20230307484A1

公开(公告)日：2023-09-28

申请号：US17701632

申请日：2022-03-22

Applicant: Omnivision Technologies, Inc.

Inventor： Shiyu Sun ,  Yuanwei Zheng ,  Gang Chen ,  Sing-Chung Hu ,  Armin Yazdani

IPC: H01L27/146

CPC classification number: H01L27/14656

Abstract: A pixel cell is formed on a semiconductor substrate having a front surface. The pixel cell includes a photodiode, a floating diffusion region, and a transfer gate. The photodiode is disposed in the semiconductor substrate. The floating diffusion region includes a first doped region disposed in the semiconductor substrate, wherein the first doped region extends from the front surface to a first junction depth in the semiconductor substrate. The transfer gate is configured to selectively couple the photodiode to the floating diffusion region controlling charge transfer between the photodiode and the floating diffusion region. The transfer gate includes a planar gate disposed on the front surface of the semiconductor substrate and a pair of vertical gate electrodes. Each vertical gate electrode extending a gate depth from the planar gate into the semiconductor substrate. The first junction depth is greater than the gate depth.