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公开(公告)号：US20160379227A1
公开(公告)日：2016-12-29
申请号：US15263111
申请日：2016-09-12
申请人： NovaSparks, Inc.
发明人： Marc Battyani
CPC分类号： G06Q30/0201 , G06Q10/1097 , G06Q40/04 , H04L67/32
摘要： High volume data processing systems and methods are provided to enable ultra-low latency processing and distribution of data. The systems and methods can be implemented to service primary trading houses where microsecond delays can significantly impact performance and value. According to one aspect, the systems and methods are configured to process data from a variety of market data sources in a variety of formats, while maintaining target latencies of less than 1 microsecond. A matrix of FPGA nodes is configured to provide ultra-low latencies while enabling deterministic and distributed processing. In some embodiments, the matrix can be configured to provide consistent latencies even during microburst conditions. Further book building operations (determination of current holdings and assets) can occur under ultra-low latency timing, providing for near instantaneous risk management, management, and execution processes, even under micro-burst conditions. In further embodiments, a FPGA matrix provides a readily expandable and convertible processing platform.
摘要翻译： 提供大容量数据处理系统和方法，以实现超低延迟处理和数据分发。 可以实施系统和方法来服务于初级贸易公司，其中微秒延迟会显着影响性能和价值。 根据一个方面，系统和方法被配置为以各种格式处理来自各种市场数据源的数据，同时保持小于1微秒的目标延迟。 FPGA节点的矩阵配置为提供超低延迟，同时实现确定性和分布式处理。 在一些实施例中，矩阵可以被配置为即使在微爆发条件期间提供一致的延迟。 进一步的书籍建筑操作（确定当前持有量和资产）可以在超低延迟时间下进行，即使在微突发条件下也能实现即时的即时风险管理，管理和执行流程。 在另外的实施例中，FPGA矩阵提供易于扩展和可转换的处理平台。
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公开(公告)号：US09443269B2
公开(公告)日：2016-09-13
申请号：US13768773
申请日：2013-02-15
申请人： NovaSparks, Inc.
发明人： Marc Battyani
IPC分类号： G06Q40/00 , G06F15/173 , G06F15/16 , G06Q40/04
CPC分类号： G06Q30/0201 , G06Q10/1097 , G06Q40/04 , H04L67/32
摘要： High volume data processing systems and methods are provided to enable ultra-low latency processing and distribution of data. The systems and methods can be implemented to service primary trading houses where microsecond delays can significantly impact performance and value. According to one aspect, the systems and methods are configured to process data from a variety of market data sources in a variety of formats, while maintaining target latencies of less than 1 microsecond. A matrix of FPGA nodes is configured to provide ultra-low latencies while enabling deterministic and distributed processing. In some embodiments, the matrix can be configured to provide consistent latencies even during micro burst conditions. Further book building operations (determination of current holdings and assets) can occur under ultra-low latency timing, providing for near instantaneous risk management, management, and execution processes, even under microburst conditions. In further embodiments, a FPGA matrix provides a readily expandable and convertible processing platform.
摘要翻译： 提供大容量数据处理系统和方法，以实现超低延迟处理和数据分发。 可以实施系统和方法来服务于初级贸易公司，其中微秒延迟会显着影响性能和价值。 根据一个方面，系统和方法被配置为以各种格式处理来自各种市场数据源的数据，同时保持小于1微秒的目标延迟。 FPGA节点的矩阵被配置为提供超低延迟，同时实现确定性和分布式处理。 在一些实施例中，矩阵可以被配置为即使在微突发条件期间也提供一致的延迟。 进一步的图书建筑操作（确定当前持有量和资产）可以在超低延迟时间内进行，即使在微暴击条件下也能即时实施即时风险管理，管理和执行流程。 在另外的实施例中，FPGA矩阵提供易于扩展和可转换的处理平台。
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公开(公告)号：US09904931B2
公开(公告)日：2018-02-27
申请号：US15263111
申请日：2016-09-12
申请人： NovaSparks, Inc.
发明人： Marc Battyani
CPC分类号： G06Q30/0201 , G06Q10/1097 , G06Q40/04 , H04L67/32
摘要： High volume data processing systems and methods are provided to enable ultra-low latency processing and distribution of data. The systems and methods can be implemented to service primary trading houses where microsecond delays can significantly impact performance and value. According to one aspect, the systems and methods are configured to process data from a variety of market data sources in a variety of formats, while maintaining target latencies of less than 1 microsecond. A matrix of FPGA nodes is configured to provide ultra-low latencies while enabling deterministic and distributed processing. In some embodiments, the matrix can be configured to provide consistent latencies even during microburst conditions. Further book building operations (determination of current holdings and assets) can occur under ultra-low latency timing, providing for near instantaneous risk management, management, and execution processes, even under micro-burst conditions. In further embodiments, a FPGA matrix provides a readily expandable and convertible processing platform.
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