公开(公告)号：US20230074722A1

公开(公告)日：2023-03-09

申请号：US17508768

申请日：2021-10-22

申请人： National Chung Cheng University

发明人： Jinn Shyan WANG ,  Chien Tung LIU ,  Chih Jung LIU

IPC分类号： G11C11/419

摘要： A memory device and an operation method thereof is disclosed. The memory device includes a SRAM cell and a power supply assist circuit connected to the SRAM cell. The power supply assist circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor receives a power supply voltage. The control terminals of the first transistor and the second transistor are connected to each other. The third transistor switches, in response to a first control signal, to connect the control terminal and the connect terminal of the second transistor. The fourth transistor switches, in response to a second control signal, to drive the control terminal of the second transistor to a system ground voltage. The fifth transistor switches, in response to a third control signal, to drive the control terminal of the first transistor to the power supply voltage.