公开(公告)号：US20230189053A1

公开(公告)日：2023-06-15

申请号：US17920912

申请日：2021-04-27

Applicant: NOKIA TECHNOLOGIES OY

Inventor： Rajesh Babu NATARAJAN ,  Gayathri TADAS ,  Kavitha NANJANGUD KEERTHI ,  Alessio CASATI

IPC: H04W28/02

CPC classification number: H04W28/0257

Abstract: An apparatus comprising: at least one processor; and at least one memory including computer program code; the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus at least to: determine (1100) that an aggregate bit rate for a network slice reached a threshold value; and adjust (1102) at least one of a maximum bit rate per terminal for the network slice or a maximum number of terminals allowed to operate on the network slice.