公开(公告)号：US20160020734A1

公开(公告)日：2016-01-21

申请号：US14870651

申请日：2015-09-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasuhide Takase

IPC: H03F1/30 ,  H03K17/687 ,  H03F3/70

CPC classification number: H03F1/301 ,  G01R29/24 ,  H03F3/70 ,  H03F2200/528 ,  H03K17/6871

Abstract: A pseudo resistor circuit and a charge amplifier include a first field effect transistor; a second field effect transistor having electrical characteristics matched with electrical characteristics of the first field effect transistor; and a voltage dividing circuit with terminal of a reference resistor electrically connected to a source terminal of the second field effect transistor. Further, a first operational amplifier with an output terminal is connected to a gate terminal of the first field effect transistor and a gate terminal of the second field effect transistor and in which midpoint voltage of the voltage dividing circuit is input into either an inverting or non-inverting input terminal and reference voltage is input into the other of the inverting and non-inverting input terminal. Furthermore, a second operational amplifier supplies voltage resulting from inversion and amplification of drain voltage of the first field effect transistor into the other terminal of the resistor.

Abstract translation: 伪电阻电路和电荷放大器包括第一场效应晶体管; 具有与第一场效应晶体管的电特性匹配的电特性的第二场效应晶体管; 以及分压电路，其具有与第二场效应晶体管的源极端子电连接的基准电阻的端子。 此外，具有输出端子的第一运算放大器连接到第一场效应晶体管的栅极端子和第二场效应晶体管的栅极端子，其中分压电路的中点电压被输入到反相或非反相 反相输入端子和参考电压输入到反相和非反相输入端子中的另一个。 此外，第二运算放大器将由第一场效应晶体管的漏极电压的反相和放大产生的电压提供给电阻器的另一端。

公开(公告)号：US10523227B2

公开(公告)日：2019-12-31

申请号：US16158330

申请日：2018-10-12

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasuhide Takase ,  Yasuyuki Matsuya ,  Eri Mizukami ,  Yuji Inagaki ,  Kazuki Mizukami ,  Nozomi Watanabe ,  Riku Yonekawa

IPC: H03M1/12 ,  H03M1/08 ,  H03M3/02 ,  H03M1/20 ,  H03M3/00

Abstract: An A/D converter includes an adder that calculates a difference between an analog input signal and a predicted value, a quantizer that quantizes the difference output from the adder to convert the analog input signal to a digital signal, a prediction filter that generates a predicted value from the digital signal output from the quantizer, and a D/A converter that converts the predicted value from a digital signal to an analog signal and output the predicted value to the adder. The predicted value before being subjected to conversion to the analog signal by the D/A converter defines and functions as an A/D converted output of the analog input signal input to the adder.

公开(公告)号：US09660592B2

公开(公告)日：2017-05-23

申请号：US14870651

申请日：2015-09-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasuhide Takase

IPC: G01R29/24 ,  H03F1/30 ,  H03F3/70 ,  H03K17/687

CPC classification number: H03F1/301 ,  G01R29/24 ,  H03F3/70 ,  H03F2200/528 ,  H03K17/6871

Abstract: A pseudo resistor circuit and a charge amplifier include a first field effect transistor; a second field effect transistor having electrical characteristics matched with electrical characteristics of the first field effect transistor; and a voltage dividing circuit with terminal of a reference resistor electrically connected to a source terminal of the second field effect transistor. Further, a first operational amplifier with an output terminal is connected to a gate terminal of the first field effect transistor and a gate terminal of the second field effect transistor and in which midpoint voltage of the voltage dividing circuit is input into either an inverting or non-inverting input terminal and reference voltage is input into the other of the inverting and non-inverting input terminal. Furthermore, a second operational amplifier supplies voltage resulting from inversion and amplification of drain voltage of the first field effect transistor into the other terminal of the resistor.

公开(公告)号：US11196441B2

公开(公告)日：2021-12-07

申请号：US15979562

申请日：2018-05-15

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasuhide Takase ,  Yasuyuki Matsuya

IPC: H03M3/00 ,  H03M1/20 ,  H03M1/80 ,  G01D5/24

Abstract: A sensor device includes an A/D converter including an adder that computes a difference between an analog input signal and a predicted value, the adder includes a capacitive adder defined by a series circuit including a capacitive charge output device and a capacitor. A capacitive component in the charge output device defines a portion of the capacitance of the capacitive adder. A digital prediction filter generates the predicted value based on an output from a quantizer. The capacitive adder computes the difference between the analog input signal from the charge output device and the predicted value. The quantizer quantizes and encodes the difference. The A/D converter performs a Δ modulation on the analog input signal which is converted into a digital signal.

公开(公告)号：US10855265B2

公开(公告)日：2020-12-01

申请号：US16672559

申请日：2019-11-04

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasuhide Takase

IPC: H03K5/24 ,  H03F3/45

Abstract: A comparison circuit includes a preliminary amplification circuit that amplifies a voltage difference between a first input voltage and a second input voltage and a latch circuit that compares magnitudes of the first input voltage and the second input voltage according to the amplified voltage difference and latch a comparison result. The preliminary amplification circuit converts the first input voltage and the second input voltage input with the falling edge timing of a clock signal into a first control signal and a second control signal, respectively that return from the reversal state at respective speeds corresponding to the first input voltage and the second input voltage. The latch circuit compares the first input voltage and the second input voltage according to the first control signal and the second control signal.

公开(公告)号：US09887689B2

公开(公告)日：2018-02-06

申请号：US15353753

申请日：2016-11-17

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasuhide Takase

IPC: H03H11/46 ,  H01L21/822 ,  H01L27/04 ,  H03F3/45

CPC classification number: H03H11/53 ,  H01L21/822 ,  H01L27/04 ,  H03F3/45475 ,  H03F2203/45511 ,  H03F2203/45512

Abstract: A pseudo resistance circuit includes a first gate voltage adjustment circuit that adjusts respective currents of first and second current sources and also adjusts a gate voltage of a second field effect transistor to equalize or substantially equalize a drain voltage of the second field effect transistor and a voltage of a first end portion of a reference resistance element and controls a drain voltage of a first field effect transistor and the drain voltage of the second field effect transistor to maintain a constant or substantially constant relationship with each other; and a second gate voltage adjustment circuit that adjusts a gate voltage of the first field effect transistor to control the gate voltage of the second field effect transistor and the gate voltage of the first field effect transistor to maintain a constant or substantially constant relationship with each other.