公开(公告)号：US20180097570A1

公开(公告)日：2018-04-05

申请号：US15722807

申请日：2017-10-02

Applicant: Michael J. Naughton ,  Juan M. Merlo-Ramirez

Inventor： Michael J. Naughton ,  Juan M. Merlo-Ramirez

IPC: H04B10/70 ,  H04B10/90

CPC classification number: H04B10/70 ,  B82Y20/00 ,  G02B5/008 ,  G02B6/107 ,  H04B10/11 ,  H04B10/90

Abstract: A nanoscale wireless communication system and device operates via in-plane information transmission between a broadcast plasmonic antenna and a receiver plasmonic antenna which mediates a three-step conversion process (surface plasmon→photon→surface plasmon) with in-plane and in-phase efficiency (plasmon→plasmon) in the free-space excitation wavelength for antenna separations in the far-field.

公开(公告)号：US10193638B2

公开(公告)日：2019-01-29

申请号：US15722807

申请日：2017-10-02

Applicant: Michael J. Naughton ,  Juan M. Merlo-Ramirez

Inventor： Michael J. Naughton ,  Juan M. Merlo-Ramirez

IPC: G05B5/00 ,  B82Y20/00 ,  H04B10/90 ,  H04B10/70 ,  H04B10/11 ,  G02B5/00

Abstract: A nanoscale wireless communication system and device operates via in-plane information transmission between a broadcast plasmonic antenna and a receiver plasmonic antenna which mediates a three-step conversion process (surface plasmon→photon→surface plasmon) with in-plane and in-phase efficiency (plasmon→plasmon) in the free-space excitation wavelength for antenna separations in the far-field.

公开(公告)号：US20230350270A1

公开(公告)日：2023-11-02

申请号：US18140384

申请日：2023-04-27

Applicant: Juan M. Merlo-Ramirez ,  Michael J. Naughton

Inventor： Juan M. Merlo-Ramirez ,  Michael J. Naughton

IPC: G02F3/00 ,  G02F1/313

CPC classification number: G02F3/00 ,  G02F1/3136

Abstract: The present technology relates to an optical logic circuit device. The optical logic circuit device includes a first input port and a second input port. A symmetric arrangement of waveguides is coupled to the first input port and the second input port. The symmetric arrangement of waveguides having a pair of topologically protected edge states that provide propagation paths through the symmetric arrangement of waveguides. An output port is coupled to the symmetric arrangement of waveguides. Methods of fabricating and using the optical logic circuit device are also disclosed.